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m16c/62 group (m16c/62p, m16c/62pt) single-chip 16-bit cmos microcomputer rej03b0001-0210z rev.2.10 nov. 07, 2003 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 1 1. overview the m16c/62 group (m16c/62p, m16c/62pt) of single-chip microcomputers are built using the high-per- formance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are ca- pable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 applications audio, cameras, office/communications/portable/industrial equipment, automobile, etc specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 2 1.2 performance outline table 1.1 to table 1.3 list performance outline of m16c/62 group (m16c/62p, m16c/62pt). table 1.1 performance outline of m16c/62 group (m16c/62p) (128-pin version) item performance m16c/62p number of basic instructions 91 instructions shortest instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.0 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) operation mode single-chip, memory expansion and microprocessor mode memory space 1 mbyte (available to 4m bytes by memory space expansion function) memory capacity see table 1.4 and 1.5 product list port input/output : 113 pins, input : 1 pin multifunction timer timer a : 16 bits x 5 channels, timer b : 16 bits x 6 channels three phase motor control circuit serial i/o 3 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 2 channels clock synchronous a-d converter 10-bit a-d converter: 1 circuit, 26 channels d-a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 8 sources, software: 4 sources, priority level: 7 levels clock generating circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), ring oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation , re-oscillation detection function voltage detection circuit available (option (4) ) supply voltage vcc1=3.0 to 5.5v, vcc2=2.7v to vcc1 (f(bclk)=24mhz) vcc1=2.7 to 5.5v, vcc2=2.7v to vcc1 (f(bclk)=10mhz) power consumption 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 8 ma (vcc1=vcc2=3v, f(bclk)=10mhz) 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) 0.7 a (vcc1=vcc2=3v, stop mode) program/erase supply voltage 3.3 0.3 v or 5.0 0.5 v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature C 20 to 85 o c C 40 to 85 o c (3) package 128-pin plastic mold qfp cpu peripheral function electric characteris- tics flash memory version notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 product code for the program and erase endurance, and operating ambient temperature. in addition 1,000 times/10,000 times are under development as of oct., 2003. please inquire about a release schedule. 4. all options are on request basis.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 3 table 1.2 performance outline of m16c/62 group (m16c/62p, m16c/62pt) (100-pin version) item performance m16c/62p m16c/62pt (note 4) number of basic instructions 91 instructions shortest instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.0 to 5.5v) 41.7ns(f(bclk)=24mhz, vcc1=4.0 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) operation mode single-chip, memory expansion and single-chip mode microprocessor mode memory space 1 mbyte (available to 4 mbytes by 1m byte memory space expansion function) memory capacity see table 1.4 to 1.7 product list port input/output : 87 pins, input : 1pin multifunction timer timer a : 16 bits x 5 channels, timer b : 16 bits x 6 channels three phase motor control circuit serial i/o 3 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 2 channels clock synchronous a-d converter 10-bit a-d converter: 1 circuit, 26 channels d-a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 8 sources, software: 4 sources, priority level: 7 levels clock generating circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), ring oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation, re-oscillation detection function voltage detection circuit available (option (5) ) absent supply voltage vcc1=3.0 to 5.5v, vcc2=2.7v to vcc1 vcc1=vcc2=4.0v to 5.5 v (f(bclk)=24mhz) (f(bclk)=24mhz) vcc1=2.7 to 5.5v, v cc2 =2.7v to vcc1 (f(bclk)=10mhz) power consumption 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 14 ma (vcc1=vcc2=5v, f(bclk)=24mhz) 8 ma (vcc1=vcc2=3v, f(bclk)=10mhz) 2.0 a (vcc1=vcc2=5v, 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) f(xcin)=32khz, wait mode) 0.8 a (vcc1=vcc2=5v, stop mode) 0.7 a (vcc1=vcc2=3v, stop mode) program/erase supply voltage 3.3 0.3 v or 5.0 0.5 v 5.0 0.5 v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature C 20 to 85 o c t version : C 40 to 85 o c C 40 to 85 o c (3) v version : C 40 to 125 o c package 100-pin plastic mold qfp, lqfp cpu peripheral function electric characteris- tics flash memory version notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 product code for the program and erase endurance, and operating ambient temperature. in addition 1,000 times/10,000 times are under development as of oct., 2003. please inquire about a release schedule. 4. use the high reliability version on vcc1 = vcc2. 5. all options are on request basis.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 4 table 1.3 performance outline of m16c/62 group (m16c/62p, m16c/62pt) (80-pin version) item performance m16c/62p m16c/62pt number of basic instructions 91 instructions shortest instruction execution time 41.7ns(f(bclk)=24mhz, vcc1=3.0 to 5.5v) 41.7ns(f(bclk)=24mhz, vcc1=4.0 to 5.5v) 100ns(f(bclk)=10mhz, vcc1=2.7 to 5.5v) operation mode single-chip mode memory space 1m byte memory capacity see t able 1.4 to 1.7 product list port input/output : 70 pins, input : 1pin multifunction timer timer a : 16 bits x 5 channels (timer a1 and a2 are internal timer) timer b : 16 bits x 6 channels (timer b1 is internal timer) serial i/o 2 channels clock synchronous, uart, i 2 c bus (1) , iebus (2) 1 channel clock synchronous, i 2 c bus (1) , iebus (2) 2 channels clock synchronous (1 channel is only for transmission) a-d converter 10-bit a-d converter: 1 circuit, 26 channels d-a converter 8 bits x 2 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 29 sources, external: 5 sources, software: 4 sources, priority level: 7 levels clock generating circuit 4 circuits main clock generation circuit (*), subclock generation circuit (*), ring oscillator, pll synthesizer (*)equipped with a built-in feedback resistor. oscillation stop detection function stop detection of main clock oscillation, re-oscillation detection function voltage detection circuit available (option (4) ) absent supply voltage vcc1=3.0 to 5.5v, (f(bclk)=24mhz) vcc1=4.0 to 5.5v, (f(bclk)=24mhz) vcc1=2.7 to 5.5v, (f(bclk)=10mhz) power consumption 14 ma (vcc1=5v, f(bclk)=24mhz) 14 ma (vcc1=5v, f(bclk)=24mhz) 8 ma (vcc1=3v, f(bclk)=10mhz) 2.0 a (vcc1=5v, 1.8 a (vcc1=3v, f(xcin)=32khz, wait mode) f(xcin)=32khz, wait mode) 0.8 a (vcc1=5v, stop mode) 0.7 a (vcc1=3v, stop mode) program/erase supply voltage 3.3 0.3 v or 5.0 0.5 v 5.0 0.5 v program and erase endurance 100 times (all area) or 1,000 times (user rom area without block 1) / 10,000 times (block a, block 1) (3) operating ambient temperature C 20 to 85 o c t version : C 40 to 85 o c C 40 to 85 o c(option) v version : C 40 to 125 o c package 80-pin plastic mold qfp cpu peripheral function electric characteris- tics flash memory version notes : 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. see table 1.8 product code for the program and erase endurance, and operating ambient temperature. in addition 1,000 times/10,000 times are under development as of oct., 2003. please inquire about a release schedule. 4. all options are on request basis.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 5 1.3 block diagram figure 1.1 is a block diagram of the m16c/62 group (m16c/62p, m16c/62pt) 128-pin and 100-pin version, figure 1.2 is a block diagram of the m16c/62 group (m16c/62p, m16c/62pt) 80-pin version. figure 1.1 m16c/62 group (m16c/62p, m16c/62pt) 128-pin and 100-pin version block diagram aaaaa a aaa a aaaaa output (timer a): 5 input (timer b): 6 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) memory rom (1) ram (2) a-d converter (10 bits x 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (8 bits x 3 channels) system clock generation circuit xin-xout xcin-xcout pll frequency synthesizer ring oscillator m16c/60 series16-bit cpu core port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) multiplier 7 8 8 port p10 port p9 port p8_5 port p8 port p7 notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. 3. ports p11 to p14 exist only in 128-pin version. 4. use m16c/62pt on vcc1= vcc2. port p5 port p4 port p3 clock synchronous serial i/o (8 bits x 2 channels) pc flg timer (16-bit) three-phase motor control circuit 8 8 8 2 port p11 port p12 port p14 port p13 (3) (4) (4) (4) (4) (4) (3) (3) (3)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 6 figure 1.2 m16c/62 group (m16c/62p, m16c/62pt) 80-pin version block diagram timer (16-bit) output (timer a): 5 input (timer b): 6 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (2 channels) uart (1 channel) system clock generation circuit xin-xout xcin-xcout pll frequency synthesizer ring oscillator m16c/60 series16-bit cpu core port p0 8 port p2 8 port p3 8 port p4 4 port p5 8 port p6 8 crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) memory 4 7 7 8 port p10 port p9 port p8 port p7 port p8_5 rom (1) ram (2) notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. 3. to use a uart2, set the crd bit in the u2c0 register to 1 (cts/rts function disabled). 4. there is no external connections for port p1, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. set the direction bits in these ports to 1 (output mode), and set the output data to 0 ( l ) using the program. clock synchronous serial i/o (8 bits x 2 channels) r0l r0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier three-phase motor control circuit a0 a1 fb (4) (4) (3)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 7 1.4 product list tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table 1.8 lists the product code of flash memory version and external rom version for m16c/62p. fig- ure 1.4 shows the marking diagram of flash memory version and external rom version for m16c/62p. please specify the mark of the mask rom version at the time of rom order. please ask separately marking of the flash memory version of m16c/62pt. 4k bytes 64k bytes m30622m8p-xxxfp 4k bytes 48k bytes m30622m6p-xxxfp 100p6q-a m30622m8p-xxxgp m30622m6p-xxxgp ram capacity rom capacity package type remarks type no. as of nov. 2003 100p6s-a mask rom version (d): under development (p): under planning 100p6q-a 100p6s-a (d) (d) (d) (d) 5k bytes 96k bytes m30622map-xxxfp m30622map-xxxgp 100p6q-a 100p6s-a 80p6s-a m30623m6p-xxxgp m30623m8p-xxxgp 80p6s-a m30623map-xxxgp 80p6s-a 12k bytes 192k bytes m30622mep-xxxfp 10k bytes 128k bytes m30620mcp-xxxfp m30622mep-xxxgp m30620mcp-xxxgp 100p6q-a 100p6s-a 100p6q-a 100p6s-a m30623mep-xxxgp 128p6q-a m30624mgp-xxxfp 100p6s-a 20k bytes m30624mgp-xxxgp 100p6q-a m30625mgp-xxxgp 128p6q-a M30622MGP-XXXFP 100p6s-a 12k bytes 256k bytes m30622mgp-xxxgp 100p6q-a 128p6q-a m30623mgp-xxxgp m30626mwp-xxxfp 100p6s-a 31k bytes m30626mwp-xxxgp 100p6q-a 128p6q-a m30627mwp-xxxgp m30624mwp-xxxfp 100p6s-a 100p6q-a 24k bytes 320k bytes m30624mwp-xxxgp 128p6q-a m30625mwp-xxxgp m30622mwp-xxxfp 100p6s-a 16k bytes m30622mwp-xxxgp 100p6q-a m30626mhp-xxxfp 100p6s-a 31k bytes m30626mhp-xxxgp 100p6q-a 128p6q-a m30623mwp-xxxgp 128p6q-a m30627mhp-xxxgp 100p6s-a m30624mhp-xxxfp 100p6q-a 24k bytes 384k bytes m30624mhp-xxxgp 128p6q-a m30625mhp-xxxgp m30622mhp-xxxfp 100p6s-a 16k bytes m30622mhp-xxxgp 100p6q-a 128p6q-a m30623mhp-xxxgp (d) (d) (d) (d) (d) (d) (d) (d) (d) m30621mcp-xxxgp 80p6s-a (d) (d) (d) (d) table 1.4 product list (1) (m16c/62p)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 8 table 1.5 product list (2) (m16c/62p) m30625fgpgp rom capacity rom capacity package type remarks type no. as of nov. 2003 128p6q-a flash memory version (d): under development (p): under planning 100p6s-a 4k bytes 64k+4k bytes m30622f8pfp m30622f8pgp 100p6q-a 10k bytes 128k+4k bytes m30620fcpfp 100p6s-a 100p6q-a m30620fcpgp 20k bytes 256k+4k bytes m30624fgpgp 100p6s-a m30624fgpfp m30626fhpfp 128p6q-a 100p6s-a 100p6q-a 31k bytes 384k+4k bytes m30626fhpgp m30627fhpgp 100p6q-a m30623f8pgp 80p6s-a 80p6s-a m30621fcpgp (d) m30626fjpfp 100p6q-a 100p6s-a 31k bytes 512k+4k bytes m30626fjpgp (p) (p) external rom version 10k bytes m30620spfp 100p6s-a (d) m30620spgp 100p6q-a (d) 4k bytes m30622spfp 100p6s-a (d) m30622spgp 100p6q-a (d) m30627fjpgp 128p6q-a (p) mask rom version m30627mjp-xxxgp m30626mjp-xxxfp 100p6q-a 100p6s-a 31k bytes 512k bytes m30626mjp-xxxgp 128p6q-a (p) (p) (p) (d)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 9 table 1.6 product list (3) (t version (m16c/62pt)) 100p6s-a 4k bytes 64k bytes m3062cm8t-xxxfp m3062cm8t-xxxgp 100p6q-a 100p6s-a 5k bytes 96k bytes m3062cmat-xxxfp m3062cmat-xxxgp 100p6q-a 100p6s-a 10k bytes 128k bytes m3062amct-xxxfp m3062amct-xxxgp 100p6q-a m3062emat-xxxgp 80p6s-a m3062em8t-xxxgp 80p6s-a m3062bmct-xxxgp 80p6s-a mask rom version 100p6s-a m3062afctfp m3062afctgp 100p6q-a 100p6s-a 31k bytes 384k+4k bytes m3062jfhtfp m3062jfhtgp 100p6q-a 10k bytes 128k+4k bytes m3062bfctgp 80p6s-a flash memory version t version (high reliability 85 c version) ram capacity rom capacity package type remarks type no. as of nov. 2003 (d): under development (p): under planning (p) (d) (d) (p) (d) (d) (p) (d) (d) (p) (d) (d) (d) (d) m3062cm6t-xxxgp m3062em6t-xxxgp m3062cm6t-xxxfp (d) (d) (p) 100p6s-a 4k bytes 48k bytes 100p6q-a 80p6s-a m3062cf8tgp 100p6q-a 4k bytes 64k bytes (d) table 1.7 product list (4) (v version (m16c/62pt)) ram capacity rom capacity package type remarks type no. as of nov. 2003 100p6s-a m3062cm8v-xxxfp 4k bytes 64k bytes m3062cm8v-xxxgp 100p6q-a 100p6s-a m3062cmav-xxxfp 5k bytes 96k bytes m3062cmav-xxxgp 100p6q-a 100p6s-a m3062amcv-xxxfp 10k bytes 128k bytes m3062amcv-xxxgp 100p6q-a m3062emav-xxxgp 80p6s-a m3062em8v-xxxgp 80p6s-a m3062bmcv-xxxgp 80p6s-a mask rom version 100p6s-a m3062afcvfp m3062afcvgp 100p6q-a 10k bytes 128k+4k bytes m3062bfcvgp 80p6s-a flash memory version (p) (p) (p) (p) (p) (p) (p) (p) (d) (d) (d) (d) 100p6s-a m3062jfhvfp m3062jfhvgp 100p6q-a 31k bytes 384k+4k bytes (p) (p) (d): under development (p): under planning 100p6s-a m3062cm6v-xxxfp 4k bytes 48k bytes m3062cm6v-xxxgp 100p6q-a m3062em6v-xxxgp 80p6s-a (p) (p) (p) v version (high reliability 125 c version)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 10 figure 1.3 type no., memory size, and package package type: fp : package 100p6s-a gp : package 80p6q-a, 100p6q-a, 128p6q-a rom no. omitted for flash memory version and external rom version memory type: m: mask rom version f: flash memory version s: external rom version type no. m 3 0 6 2 6 m h p C x x x f p m16c/62 group m16c family shows ram capacity, pin count, etc numeric : m16c/62p alphabet : m16c/62pt rom capacity: 6: 48k bytes 8: 64k bytes a: 96k bytes c: 128k bytes e: 192k bytes g: 256k bytes w: 320k bytes h: 384k bytes j: 512k bytes classification p : m16c/62p t : t version (m16c/62pt) v : v version (m16c/62pt)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 11 product code package internal rom (user rom area without block 1) program and erase endurance temperature range internal rom (block a, block 1) operating ambient temperature temperature range lead-free lead-included d3 d5 d7 d9 u3 u5 u7 u9 100 1,000 100 1,000 0 c to 60 c 100 10,000 100 10,000 0 c to 60 c 0 c to 60 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c lead-free d3 d5 u3 u5 -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c lead-included flash memory version external rom version program and erase endurance table 1.8 product code of flash memory version and external rom version for m16c/62p m1 6 c m30626fhpfp bd5 xxxxxxx type no. (see figure 1.3 type no., memory size, and package ) chip version and product code. b : shows chip version. henceforth, whenever it changes a version, it continues with b, c, and d. d5 : shows product code. (see table 1.8 product code .) data code seven digits the product without marking of chip version of the flash memory version and the rom external version corresponds to the chip version a . figure 1.4 marking diagram of flash memory version and external rom version for m16c/62p (top view)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 12 1.5 pin configuration figures 1.5 to 1.8 show the pin configurations (top view). package: 128p6q-a figure 1.5 pin configuration (top view) pin configuration (top view) notes: 1. p7_0 and p7_1 are n channel open-drain output pins. 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 31 32 33 34 35 36 37 66 67 68 69 70 71 72 38 65 64 103 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/rdy/clkout p4_7/cs3 p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p4_5/cs1 p4_6/cs2 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) p8_4/int2/zp p8_1/ta4in/u p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 vref avcc p9_7/adtrg/sin4 p14_1 p14_0 p13_7 p13_6 p13_5 p13_4 p1_3/d11 p1_4/d12 p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p12_4 p12_3 p11_3 p11_2 p11_1 p11_0 vcc1 vss p13_0 p13_1 p13_2 p13_3 p12_5 p12_6 p12_7 p11_4 p11_5 p11_6 p11_7 p12_2 p12_1 p12_0 m16c/62 group (m16c/62p)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 13 figure 1.6 pin configuration (top view) package: 100p6s-a pin configuration (top view) 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p7_2/clk2/ta1out/v p8_2/int0 p7_1/rxd2/scl2/ta0in/tb5in (1) p8_3/int1 p8_5/nmi p9_7/adtrg/sin4 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p7_0/txd2/sda2/ta0out (1) p8_4/int2/zp p8_1/ta4in/u p7_3/cts2/rts2/ta1in/v p7_5/ta2in/w p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 m16c/62 group ( m16c/62p, m16c/62pt ) notes: 1. p7_0 and p7_1 are n channel open-drain output pins.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 14 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p9_6/anex1/sout4 p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p9_7/adtrg/sin4 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p8_4/int2/zp p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out (1) p7_5/ta2in/w p7_3/cts2/rts2/ta1in/v p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p8_1/ta4in/u figure 1.7 pin configuration (top view) package: 100p6q-a pin configuration (top view) m16c/62 group ( m16c/62p, m16c/62pt ) notes: 1. p7_0 and p7_1 are n channel open-drain output pins.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 15 figure 1.8 pin configuration (top view) package: 80p6s-a pin configuration (top view) 1 2 3 4 5 6 7 8 9 1011121314151617181920 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 56 p4_2 p4_3 p5_6 p5_5 p5_4 p5_3 p5_2 p5_7/clkout p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p7_1/rxd2/scl2/ta0in/tb5in (1) p5_0 p5_1 p7_0/txd2/sda2/ta0out (1) p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p4_0 p4_1 vcc1 xin xout vss reset cnvss(byte) p8_7/xcin p8_6/xcout p7_6/ta3out p7_7/ta3in p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/clk4 p8_2/int0 p8_3/int1 p8_1/ta4in p8_4/int2/zp p8_0/ta4out p8_5/nmi p0_0/an0_0 p0_1/an0_1 p0_2/an0_2 p0_3/an0_3 p0_4/an0_4 p0_5/an0_5 p0_6/an0_6 p0_7/an0_7 vref avss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p10_4/an4/ki0 p10_5/an5/ki1 p10_6/an6/ki2 p10_7/an7/ki3 p9_6/anex1/sout4 p9_0/tb0in/clk3 p2_0/an2_0 p2_1/an2_1 p2_2/an2_2 p2_4/an2_4 p2_5/an2_5 p2_6/an2_6 p2_7/an2_7 p2_3/an2_3 p9_7/adtrg/sin4 p9_2/tb2in/sout3 m16c/62 group ( m16c/62p, m16c/62pt ) notes: 1. p7_0 and p7_1 are n channel open-drain output pins.
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 16 1.6 pin description table 1.9 pin description (100-pin and 128-pin version) (1) apply 2.7 to 5.5 v to the vcc1 and vcc2 pins and 0 v to the v ss pin. the vcc apply condition is that vcc1 vcc2. (2) applies the power supply for the a-d converter. connect the avcc pin to vcc1. connect the avss pin to vss. the microcomputer is in a reset state when applying "l" to the this pin. switches processor mode. connect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. switches the data bus in external memory space. the data bus is 16 bits long when the this pin is held "l" and 8 bits long when the this pin is held "h". set it to either one. connect this pin to v ss when an single-chip mode. inputs and outputs data (d0 to d7) when these pins are set as the separate bus. inputs and outputs data (d8 to d15) when external 16-bit data bus is set as the separate bus. output address bits (a0 to a19). input and output data (d0 to d7) and output address bits (a0 to a7) by time- sharing when external 8-bit data bus are set as the multiplexed bus. input and output data (d0 to d7) and output address bits (a8 to a15) by time- sharing when external 16-bit data bus are set as the multiplexed bus. ________ ________ ________ ________ output cs0 to cs3 signals. cs0 to cs3 are chip-select signals to specify an external space. ________ _________ ______ ________ _____ ________ _________ _______ ______ output wrl, wrh, (wr, bhe), rd signals. wrl and wrh or bhe and wr can be switched by program. ________ _________ _____ ? wrl, wrh and rd are selected ________ the wrl signal becomes "l" by writing data to an even address in an external memory space. _________ the wrh signal becomes "l" by writing data to an odd address in an external memory space. _____ the rd pin signal becomes "l" by reading data in an external memory space. ______ ________ _____ ? wr, bhe and rd are selected ______ the wr signal becomes "l" by writing data in an external memory space. _____ the rd signal becomes "l" by reading data in an external memory space. ________ the bhe signal becomes "l" by accessing an odd address. ______ ________ _____ select wr, bhe and rd for an external 8-bit data bus. ale is a signal to latch the address. __________ while the hold pin is held "l", the microcomputer is placed in a hold state. _________ in a hold state, hlda outputs a "l" signal. ________ while applying a "l" signal to the rdy pin, the microcomputer is placed in a wait state. vcc1, vcc2 vss avcc avss ____________ reset cnvss byte d0 to d7 d8 to d15 a0 to a19 a0/d0 to a7/d7 a1/d0 to a8/d7 ______ ______ cs0 to cs3 ________ ______ wrl/wr _________ ________ wrh/bhe _____ rd ale __________ hold __________ hlda ________ rdy power supply input analog power supply input reset input cnvss external data bus width select input bus control pins (4) i i i i i i/o i/o o i/o i/o o o o i o i - vcc1 vcc1 vcc1 vcc1 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 power signal name pin name i/o type description supply i : input o : output i/o : input and output power supply : power supplies which relate to the external bus pins are separated as vcc2, thus they can be inter- faced using the different voltage as vcc1. notes: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted. 2. in m16c/62pt, apply 2.7 to 5.5 v to the vcc1 and vcc2 pins. also the apply condition is that vcc1 vcc2. 3. when use vcc1 vcc2, contacts due to some points or restrictions to be checked. 4. this pin function is not in m16c/62pt.
m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 17 1. overview table 1.10 pin description (100-pin and 128-pin version) (2) xin xout xcin xcout bclk clkout ________ ________ int0 to int5 _______ nmi _____ ______ ki0 to ki3 ta0out to ta4out ta0in to ta4in zp tb0in to tb5in __ __ u, u, v, v, __ w, w __________ ________ cts0 to cts2 ________ ________ rts0 to rts2 clk0 to clk4 rxd0 to rxd2 sin3, sin4 txd0 to txd2 sout3, sout4 clks1 sda0 to sda2 scl0 to scl2 main clock input main clock output sub clock input sub clock output bclk output (2) clock output ______ int interrupt input _______ nmi interrupt input key input interrupt input timer a timer b three-phase motor control output serial i/o i 2 c mode vcc1 vcc1 vcc1 vcc1 vcc2 vcc2 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 i o i o o o i i i i/o i i i o i o i/o i i o o o i/o i/o i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (3) . to use the external clock, input the clock from xin and leave xout open. i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (3) . to use the external clock, input the clock from xcin and leave xcout open. outputs the bclk signal. the clock of the same cycle as fc, f8, or f32 is outputted. ______ input pins for the int interrupt _______ input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. input pins for the key input interrupt these are timer a0 to timer a4 i/o pins. (except the output of taout for the n- channel open drain output.) these are timer a0 to timer a4 input pins. input pin for the z-phase. these are timer b0 to timer b5 input pins. these are three-phase motor control output pins. these are send control input pins. these are receive control output pins. these are transfer clock i/o pins. these are serial data input pins. these are serial data input pins. these are serial data output pins. (except txd2 for the n-channel open drain output.) these are serial data output pins. this is output pin for transfer clock output from multiple pins function. these are serial data i/o pins. (except sda2 for the n-channel open drain output.) these are transfer clock i/o pins. (except scl2 for the n-channel open drain output.) i : input o : output i/o : input and output notes: 1. when use vcc1 vcc2, contacts due to some points or restrictions to be checked. 2. this pin function is not in m16c/62pt. 3. ask the oscillator maker the oscillation characteristic. power signal name pin name i/o type description supply
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 18 table 1.11 pin description (100-pin and 128-pin version) (3) vref an0 to an7, an0_0 to an0_7, an2_0 to an2_7 ___________ adtrg anex0 anex1 da0, da1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7 (2) , p13_0 to p13_7 (2) p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7 (2) p8_0 to p8_4, p8_6, p8_7, p14_0, p14_1 (2) p8_5 reference voltage input a-d converter d-a converter i/o port input port vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc2 vcc1 vcc1 vcc1 applies the reference voltage for the a-d converter and d-a converter. analog input pins for the a-d converter this is an a-d trigger input pin. this is the extended analog input pin for the a-d converter, and is the output in external op-amp connection mode. this is the extended analog input pin for the a-d converter. this is the input pin for the d-a converter. 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. 8-bit i/o ports having equivalent functions to p0. (except p7_0 and p7_1 for the n-channel open drain output.) i/o ports having equivalent functions to p0. _______ input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. i i i i/o i o i/o i/o i/o i i : input o : output i/o : input and output notes: 1. when use vcc1 vcc2, contacts due to some points or restrictions to be checked. 2. ports p11 to p14 are provided in the 128-pin version only. power signal name pin name i/o type description supply
m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 19 1. overview apply 2.7 to 5.5 v to the vcc1 pin and 0 v to the vss pin. (2) applies the power supply for the a-d converter. connect the avcc pin to vcc1. connect the avss pin to vss. the microcomputer is in a reset state when applying "l" to the this pin. switches processor mode. connect this pin to v ss to when after a reset to start up in single-chip mode. connect this pin to v cc1 to start up in micropro- cessor mode. as for the byte pin of the 80-pin versions, pull-up processing is performed within the microcomputer. i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (3) . to use the external clock, input the clock from xin and leave xout open. i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (3) . to use the external clock, input the clock from xcin and leave xcout open. the clock of the same cycle as fc, f8, or f32 is outputted. ______ input pins for the int interrupt _______ input pin for the nmi interrupt. input pins for the key input interrupt these are timer a0, timer a3 and timer a4 i/o pins. (except the output of taout for the n-channel open drain output.) these are timer a0, timer a3 and timer a4 input pins. input pin for the z-phase. these are timer b0, timer b2 to timer b5 input pins. these are send control input pins. these are receive control output pins. these are transfer clock i/o pins. these are serial data input pins. these are serial data input pins. these are serial data output pins. (except txd2 for the n-channel open drain output.) these are serial data output pins. this is output pin for transfer clock output from multiple pins function. these are serial data i/o pins. (except sda2 for the n-channel open drain output.) these are transfer clock i/o pins. (except scl2 for the n-channel open drain output.) vcc1, vss avcc, avss ____________ reset cnvss (byte) xin xout xcin xcout clkout ________ ________ int0 to int2 _______ nmi ______ ______ ki0 to ki3 ta0out, ta3out, ta4out ta0in, ta3in, ta4in zp tb0in, tb2in to tb5in _________ _________ cts0, cts2 _________ _________ rts0, rts2 clk0, clk1, clk3, clk4 rxd0 to rxd2 sin4 txd0 to txd4 sout3, sout4 clks1 sda0 to sda2 scl0 to scl2 power supply input analog power supply input reset input cnvss main clock input main clock output sub clock input sub clock output clock output ______ int interrupt input _______ nmi interrupt input key input interrupt input timer a timer b serial i/o i 2 c mode i i i i i o i o o i i i i/o i i i i o i/o i i o o o i/o i/o - vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc2 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 power signal name pin name i/o type description supply i : input o : output i/o : input and output notes: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted. 2. in m16c/62pt, apply 4.0 to 5.5 v to the vcc1 pin. 3. ask the oscillator maker the oscillation characteristic. table 1.12 pin description (80-pin version) (1)
1. overview m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 20 table 1.13 pin description (80-pin version) (2) vref an0 to an7, an0_0 to an0_7, an2_0 to an2_7 ___________ adtrg anex0 anex1 da0, da1 p0_0 to p0_7, p2_0 to p2_7, p3_0 to p3_7, p5_0 to p5_7, p6_0 to p6_7, p10_0 to p10_7 p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7 p4_0 to p4_3, p7_0, p7_1, p7_6, p7_7 p8_5 reference voltage input a-d converter d-a converter i/o port input port vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 applies the reference voltage for the a-d converter and d-a converter. analog input pins for the a-d converter this is an a-d trigger input pin. this is the extended analog input pin for the a-d converter, and is the output in external op-amp connection mode. this is the extended analog input pin for the a-d converter. this is the input pin for the d-a converter 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. i/o ports having equivalent functions to p0. i/o ports having equivalent functions to p0. (except p7_0 and p7_1 for the n-channel open drain output.) _______ input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. i i i i/o i o i/o i/o i/o i i : input o : output i/o : input and output notes: 1. there is no external connections for port p1, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. set the direction bits in these ports to 1 (input mode), and set the output data to 0 ( l ) using the program. power signal name pin name i/o type description supply
m16c/62 group (m16c/62p, m16c/62pt) page 21 2. central processing unit (cpu) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1 central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and logic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (1) address registers (1) frame base registers (1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register notes: 1. these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa aa aa aa aa a a aaaaaaa aaaaaaa aa aa a a aa aa aa aa aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
m16c/62 group (m16c/62p, m16c/62pt) 2. central processing unit (cpu) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 22 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0 . 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0 . 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1 . 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0 . 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0 , and are enabled when the i flag is 1 . the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0 ; usp is selected when the u flag is 1 . the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
m16c/62 group (m16c/62p, m16c/62pt) page 23 3. memory 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r 3. memory figure 3.1 is a memory map of the m16c/62p group. the address space extends the 1m bytes from address 00000h to fffffh. the internal rom is allocated in a lower address direction beginning with address fffffh. for example, a 64-kbyte internal rom is allocated to the addresses from f0000h to fffffh. as for the flash memory version, 4-kbyte space (block a) exists in 0f000h to 0ffffh. 4-kbyte space is mainly for storing data. in addition to storing data, 4-kbyte space also can store programs. the fixed interrupt vector table is allocated to the addresses from fffdch to fffffh. therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 10-kbyte internal ram is allocated to the addresses from 00400h to 02bffh. in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the srf is allocated to the addresses from 00000h to 003ffh. peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocated to the addresses from ffe00h to fffdbh. this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 series software manual . in memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. use m16c/62p (80-pin version) and m16c/62pt in single-chip mode. the memory expan- sion and microprocessor modes cannot be used. figure 3.1 memory map 00000h xxxxxh aaaaaa a aaaa a a aaaa a a aaaa a a aaaa a aaaaaa external area internal rom (program area) sfr internal ram reserved area (1) reserved area (2) fffdch notes: 1. during memory expansion and microprocessor modes, can not be used. 2. in memory expansion mode, can not be used. 3. as for the flash memory version, 4-kbyte space (block a) exists. 4. shown here is a memory map for the case where the pm10 bit in the pm1 register is 1 and the pm13 bit in the pm1 register is 1 . undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi 4k bytes 013ffh 02bffh 017ffh address xxxxxh 033ffh 10k bytes 5k bytes 12k bytes size address yyyyyh size f0000h e8000h f4000h 96k bytes 48k bytes 64k bytes reserved area external area 00400h 10000h 27000h 28000h 80000h yyyyyh fffffh e0000h 256k bytes 128k bytes 192k bytes d0000h 320k bytes c0000h 384k bytes b0000h a0000h 512k bytes 80000h 063ffh 053ffh 07fffh 24k bytes 20k bytes 31k bytes internal ram internal rom (3) 043ffh 16k bytes ffe00h fffffh internal rom (data area) (3) 0ffffh 0f000h
m16c/62 group (m16c/62p, m16c/62pt) 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 24 dma0 control register dm0con 00000x00b dma0 transfer counter tcr0 xxh xxh dma1 control register dm1con 00000x00b dma1 source pointer sar1 xxh xxh xxh dma1 transfer counter tcr1 xxh xxh dma1 destination pointer dar1 xxh xxh xxh watchdog timer start register wdts xxh watchdog timer control register wdc 00xxxxxxb (4) processor mode register 0 (2) pm0 00000000b(cnvss pin is l ) 00000011b(cnvss pin is h ) chip select control register (6) csr 00000001b system clock control register 0 cm0 01001000b system clock control register 1 cm1 00100000b address match interrupt enable register aier xxxxxx00b protect register prcr xx000000b processor mode register 1 pm1 00001000b dma0 destination pointer dar0 xxh xxh xxh notes : 1. the blank areas are reserved and cannot be accessed by users. 2. the pm00 and pm01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. 3. the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. 4. the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 when the input voltage at the v cc1 pin drops to vdet2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enabl e 5. this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 6. this register cannot be used by m16c/62pt. x : nothing is mapped to this bit data bank register (6) dbr 00h oscillation stop detection register (3) cm2 0000x000b chip select expansion control register (6) cse 00h pll control register 0 plc0 0001x010b processor mode register 2 pm2 xxx00000b 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000ah 000bh 000ch 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh address register symbol after reset address match interrupt register 0 rmad0 00h 00h x0h address match interrupt register 1 rmad1 00h 00h x0h dma0 source pointer sar0 xxh xxh xxh voltage detection register 1 (5, 6) vcr1 00001000b voltage detection register 2 (5, 6) vcr2 00h voltage down detection interrupt register (6) d4int 00h 4. sfr
m16c/62 group (m16c/62p, m16c/62pt) page 25 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r timer a1 interrupt control register ta1ic xxxxx000b uart0 transmit interrupt control register s0tic xxxxx000b timer a0 interrupt control register ta0ic xxxxx000b timer a2 interrupt control register ta2ic xxxxx000b uart0 receive interrupt control register s0ric xxxxx000b uart1 transmit interrupt control register s1tic xxxxx000b uart1 receive interrupt control register s1ric xxxxx000b dma1 interrupt control register dm1ic xxxxx000b dma0 interrupt control register dm0ic xxxxx000b key input interrupt control register kupic xxxxx000b a-d conversion interrupt control register adic xxxxx000b uart2 bus collision detection interrupt control register bcnic xxxxx000b uart2 transmit interrupt control register s2tic xxxxx000b uart2 receive interrupt control register s2ric xxxxx000b int1 interrupt control register int1ic xx00x000b timer b0 interrupt control register tb0ic xxxxx000b timer b2 interrupt control register tb2ic xxxxx000b timer a3 interrupt control register ta3ic xxxxx000b int2 interrupt control register int2ic xx00x000b int0 interrupt control register int0ic xx00x000b timer b1 interrupt control register tb1ic xxxxx000b timer a4 interrupt control register ta4ic xxxxx000b int3 interrupt control register int3ic xx00x000b timer b5 interrupt control register tb5ic xxxxx000b timer b4 interrupt control register, uart1 bus collision detection interrupt control register tb4ic, u1bcnic xxxxx000b timer b3 interrupt control register, uart0 bus collision detection interrupt control register tb3ic, u0bcnic xxxxx000b si/o4 interrupt control register (s4ic), int5 interrupt control register s4ic , int5ic xx00x000b si/o3 interrupt control register, int4 interrupt control register s3ic , int4ic xx00x000b notes : 1. the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh address register symbol after reset
m16c/62 group (m16c/62p, m16c/62pt) 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 26 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01afh 01b0h 01b1h 01b2h 01b3h 01b4h 01b5h 01b6h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh 00c0h to 02afh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h to 032fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033ah 033bh 033ch 033dh 033eh 033fh notes : 1. the blank areas are reserved and cannot be accessed by users. 2. this register is included in the flash memory version. x : nothing is mapped to this bit peripheral clock select register pclkr 00000011b flash memory control register 0 (2) fmr0 xx000001b flash memory control register 1 (2) fmr1 0x00xx0xb address match interrupt register 2 rmad2 00h 00h x0h address match interrupt register 3 rmad3 00h 00h x0h address match interrupt enable register 2 aier2 xxxxxx00b address register symbol after reset flash identification register (2) fidr xxxxxx00b
m16c/62 group (m16c/62p, m16c/62pt) page 27 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r address register symbol after reset 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034ah 034bh 034ch 034dh 034eh 034fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035ah 035bh 035ch 035dh 035eh 035fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036ah 036bh 036ch 036dh 036eh 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037ah 037bh 037ch 037dh 037eh 037fh timer a1-1 register ta11 xxh xxh timer a2-1 register ta21 xxh xxh dead time timer dtt xxh timer b2 interrupt occurrence frequency set counter ictb2 xxh three-phase pwm control register 0 invc0 00h three-phase pwm control register 1 invc1 00h three-phase output buffer register 0 idb0 00h three-phase output buffer register 1 idb1 00h timer b3 register tb3 xxh xxh timer b4 register tb4 xxh xxh timer b5 register tb5 xxh xxh timer b3, 4, 5 count start flag tbsr 000xxxxxb timer b3 mode register tb3mr 00xx0000b timer b4 mode register tb4mr 00xx0000b timer b5 mode register tb5mr 00xx0000b interrupt cause select register ifsr 00h si/o3 transmit/receive register s3trr xxh si/o4 transmit/receive register s4trr xxh si/o3 control register s3c 01000000b si/o3 bit rate generator s3brg xxh si/o4 bit rate generator s4brg xxh si/o4 control register s4c 01000000b uart2 special mode register u2smr x0000000b uart2 receive buffer register u2rb xxh xxh uart2 transmit buffer register u2tb xxh xxh uart2 transmit/receive control register 0 u2c0 00001000b uart2 transmit/receive mode register u2mr 00h uart2 transmit/receive control register 1 u2c1 00000010b uart2 bit rate generator u2brg xxh timer a4-1 register ta41 xxh xxh uart2 special mode register 2 u2smr2 x0000000b notes : 1. the blank areas are reserved and cannot be accessed by users. x : nothing is mapped to this bit uart2 special mode register 3 u2smr3 000x0x0xb interrupt cause select register 2 ifsr2a 00xxxxxxb uart0 special mode register 2 u0smr2 x0000000b uart0 special mode register u0smr x0000000b uart0 special mode register 3 u0smr3 000x0x0xb uart0 special mode register 4 u0smr4 00h uart1 special mode register 2 u1smr2 x0000000b uart1 special mode register u1smr x0000000b uart1 special mode register 3 u1smr3 000x0x0xb uart1 special mode register 4 u1smr4 00h uart2 special mode register 4 u2smr4 00h
m16c/62 group (m16c/62p, m16c/62pt) 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 28 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038ah 038bh 038ch 038dh 038eh 038fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039ah 039bh 039ch 039dh 039eh 039fh 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh timer a0 register ta0 xxh xxh timer a1 register ta1 xxh xxh timer a2 register ta2 xxh xxh timer b0 register tb0 xxh xxh timer b1 register tb1 xxh xxh timer b2 register tb2 xxh xxh count start flag tabsr 00h one-shot start flag onsf 00h timer a0 mode register ta0mr 00h timer a1 mode register ta1mr 00h timer a2 mode register ta2mr 00h timer b0 mode register tb0mr 00xx0000b timer b1 mode register tb1mr 00xx0000b timer b2 mode register tb2mr 00xx0000b up-down flag udf 00h (2) timer a3 register ta3 xxh xxh timer a4 register ta4 xxh xxh timer a3 mode register ta3mr 00h timer a4 mode register ta4mr 00h trigger select register trgsr 00h clock prescaler reset flag cpsrf 0xxxxxxxb uart0 transmit/receive mode register u0mr 00h uart0 transmit buffer register u0tb xxh xxh uart0 receive buffer register u0rb xxh xxh uart1 transmit/receive mode register u1mr 00h uart1 transmit buffer register u1tb xxh xxh uart1 receive buffer register u1rb xxh xxh uart0 bit rate generator u0brg xxh uart0 transmit/receive control register 0 u0c0 00001000b uart0 transmit/receive control register 1 u0c1 00000010b uart1 bit rate generator u1brg xxh uart1 transmit/receive control register 0 u1c0 00001000b uart1 transmit/receive control register 1 u1c1 00000010b dma1 request cause select register dm1sl 00h dma0 request cause select register dm0sl 00h crc data register crcd xxh xxh crc input register crcin xxh uart transmit/receive control register 2 ucon x0000000b notes : 1.the blank areas are reserved and cannot be accessed by users. 2. bits 7 to 5 in the up-down flag are 0 by reset. however, the values in these bits when read are indeterminate. x : nothing is mapped to this bit timer b2 special mode register tb2sc xxxxxx00b address register symbol after reset
m16c/62 group (m16c/62p, m16c/62pt) page 29 4. sfr 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r 03c0h 03c1h 03c2h 03c3h 03c4h 03c5h 03c6h 03c7h 03c8h 03c9h 03cah 03cbh 03cch 03cdh 03ceh 03cfh 03d0h 03d1h 03d2h 03d3h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah 03dbh 03dch 03ddh 03deh 03dfh 03e0h 03e1h 03e2h 03e3h 03e4h 03e5h 03e6h 03e7h 03e8h 03e9h 03eah 03ebh 03ech 03edh 03eeh 03efh 03f0h 03f1h 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh notes : 1. the blank areas are reserved and cannot be accessed by users. 2. at hardware reset 1 or hardware reset 2, the register is as follows: ? 00000000b where l is inputted to the cnv ss pin ? 00000010b where h is inputted to the cnv ss pin at software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: ? 00000000b where the pm01 to pm00 bits in the pm0 register are 00b (single-chip mode) ? 00000010b where the pm01 to pm00 bits in the pm0 register are 01b (memory expansion mode) or 11b (microprocessor mode) x : nothing is mapped to this bit a-d register 7 ad7 xxh xxh a-d register 0 ad0 xxh xxh a-d register 1 ad1 xxh xxh a-d register 2 ad2 xxh xxh a-d register 3 ad3 xxh xxh a-d register 4 ad4 xxh xxh a-d register 5 ad5 xxh xxh a-d register 6 ad6 xxh xxh a-d control register 0 adcon0 00000xxxb d-a register 0 da0 00h d-a register 1 da1 00h d-a control register dacon 00h a-d control register 2 adcon2 00h a-d control register 1 adcon1 00h port p0 register p0 xxh port p0 direction register pd0 00h port p1 register p1 xxh port p1 direction register pd1 00h port p2 register p2 xxh port p2 direction register pd2 00h port p3 register p3 xxh port p3 direction register pd3 00h port p4 register p4 xxh port p4 direction register pd4 00h port p5 register p5 xxh port p5 direction register pd5 00h port p6 register p6 xxh port p6 direction register pd6 00h port p7 register p7 xxh port p7 direction register pd7 00h port p8 register p8 xxh port p8 direction register pd8 00x00000b port p9 register p9 xxh port p9 direction register pd9 00h port p10 register p10 xxh port p10 direction register pd10 00h pull-up control register 0 pur0 00h pull-up control register 1 pur1 00000000b 00000010b pull-up control register 2 pur2 00h port control register pcr 00h port p14 control register pc14 xx00xxxxb pull-up control register 3 pur3 00h port p11 register p11 xxh port p12 register p12 xxh port p13 register p13 xxh port p11 direction register pd11 00h port p12 direction register pd12 00h port p13 direction register pd13 00h register symbol after reset address (2)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 30 table 5.1 absolute maximum ratings o p e r a t i n g a m b i e n t t e m p e r a t u r e p a r a m e t e runit v r e f , x i n i n p u t v o l t a g e a n a l o g s u p p l y v o l t a g e supply voltage o u t p u t v o l t a g e x o u t v o -0.3 to v cc1 +0.3 (1) - 0 . 3 t o v c c 1 + 0 . 3 ( 1 ) p d power dissipation s t o r a g e t e m p e r a t u r e r a t e d v a l u e v v v c o n d i t i o n v i a v c c v c c 1 , v c c 2 t s t g t o p r s y m b o l mw p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 7 _ 0 , p 7 _ 1 p 7 _ 0 , p 7 _ 1 - 0 . 3 t o 6 . 5 v v r e s e t , c n v s s , b y t e , v cc1 =av cc v cc1 =av cc - 0 . 3 t o 6 . 5 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , s u p p l y v o l t a g e - 0 . 3 t o v c c 1 + 0 . 1v v c c 2 v cc2 p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 - 0 . 3 t o v c c 2 + 0 . 3 ( 1 ) v v p11_0 to p11_7, p14_0, p14_1, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p12_0 to p12_7, p13_0 to p13_7 -0.3 to v cc2 +0.3 (1) v - 0 . 3 t o 6 . 5 - 6 5 t o 1 5 0 300 - 2 0 t o 8 5 / - 4 0 t o 8 5 - 0 . 3 t o 6 . 5 c c notes: 1. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. -40 c < t opr 85 c w h e n t h e m i c r o c o m p u t e r i s o p e r a t i n g f l a s h p r o g r a m e r a s e 0 t o 6 0 5. electrical characteristics 5.1 electrical characteristics (m16c/62p)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 31 2 . 75 . 5 t y p .m a x . unit p a r a m e t e r v c c 1 , v c c 2 5.0 s u p p l y v o l t a g e ( v c c 1 v c c 2 ) s y m b o l min. s t a n d a r d a n a l o g s u p p l y v o l t a g e v c c 1 a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h i oh (avg) h i g h a v e r a g e o u t p u t c u r r e n t ma ma v s s a v s s 0 . 8 v c c 2 v v v v v v c c 2 0 . 2 v c c 2 0.2v cc1 0 0 0 l o w i n p u t v o l t a g e 0.16v cc2 i oh (peak) high peak output current h i g h i n p u t v o l t a g e -5.0 -10.0 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 3 _ 1 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 v v 0 . 8 v c c 2 0 . 5 v c c 2 v c c 2 v c c 2 ( d a t a i n p u t d u r i n g m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s ) p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 ( d u r i n g s i n g l e - c h i p m o d e ) p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 l o w p e a k o u t p u t c u r r e n t 1 0 . 0 5.0 m a low average output current i o l ( p e a k ) ma i ol (avg) v p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 7 _ 0 , p 7 _ 1 0 . 8 v c c 1 6 . 5v v i l p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 notes: 1. referenced to v cc1 = v cc2 = 2.7 to 5.5v at t opr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2. sv cc indicates the minimum time gradient until v cc1 reaches 2.7v. 3. the mean output current is the mean value within 100ms. 4. the total i ol (peak) for ports p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14_0 and p14_1 must be 80ma max. the total i ol (peak) for ports p3, p4, p5, p6, p7, p8_0 to p8_4, p12, and p13 must be 80ma max. the total i oh (peak) for ports p0, p1, and p2 must be -40ma max. the total i oh (peak) for ports p3, p4, p5, p12, and p13 must be -40ma max. the total i oh (peak) for ports p6, p7, and p8_0 to p8_4 must be -40ma max. the total i oh (peak) for ports p8_6, p8_7, p9, p10, p11, p14_0, and p14_1 must be -40ma max. 5. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. 0 . 8 v c c 1 v v cc1 p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , x i n , r e s e t , c n v s s , b y t e p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , p 3 _ 1 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 ( d u r i n g s i n g l e - c h i p m o d e ) v 0.2v cc2 0 (data input during memory expansion and microprocessor modes) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset, cnvss, byte p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , f ( r i p p l e ) ( 2 ) p o w e r s u p p l y r i p p l e a l l o w a b l e f r e q u e n c y p o w e r s u p p l y r i p p l e a l l o w a b l e a m p l i t u d e v o l t a g e v p - p ( r i p p l e ) ( 2 ) (v cc1 =5v) (v cc1 =3v) p o w e r s u p p l y r i p p l e r i s i n g / f a l l i n g g r a d i e n t v c c ( | ? v / ? t | ) ( 2 ) (v cc1 =5v) (v cc1 =3v) p o w e r s u p p l y r i s i n g g r a d i e n t s v c c ( 2 ) 1 0 0.5 0. 3 0. 3 0. 3 0 . 0 5 m h z v v v / m s v / m s v / m s table 5.2 recommended operating conditions (1) (1) v p-p(ripple) f (ripple) sv cc t v v cc1 0v
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 32 table 5.3 recommended operating conditions (2) (1) main clock input oscillation frequency 16.0 0.0 f(xin) operating maximum frequency [mhz] v cc1 [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 20 x v cc1 -44mhz pll clock oscillation frequency 24.0 0.0 f(pll) operating maximum frequency [mhz] v cc1 [v] (pll clock oscillation) 5.5 10.0 2.7 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 3.0 46.67 x v cc1 -116mhz t y p .max. u n i t p a r a m e t e r s y m b o l min. s t a n d a r d no t e s: 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 2 . 7 t o 5 . 5 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 . r e l a t i o n s h i p b e t w e e n m a i n c l o c k o s c i l l a t i o n f r e q u e n c y , p l l c l o c k o s c i l l a t i o n f r e q u e n c y a n d s u p p l y v o l t a g e . f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y ( 2 ) 2 0 x v c c 1 - 4 4 v c c 1 = 3 . 0 t o 5 . 5 v v c c 1 = 2 . 7 t o 3 . 0 v 0 0 mhz mhz 1 6 f ( x c i n )s u b - c l o c k o s c i l l a t i o n f r e q u e n c y khz 50 3 2 . 7 6 8 f ( r i n g ) r i n g o s c i l l a t i o n f r e q u e n c y mhz 1 f ( p l l ) p l l c l o c k o s c i l l a t i o n f r e q u e n c y ( 2 ) 4 6 . 6 7 x v c c 1 - 1 1 6 v c c 1 = 3 . 0 t o 5 . 5 v v c c 1 = 2 . 7 t o 3 . 0 v 1 0 1 0 mhz mhz 2 4 f (bclk) cpu operation clock 0 mhz 24 t s u ( p l l ) p l l f r e q u e n c y s y n t h e s i z e r s t a b i l i z a t i o n w a i t t i m e v c c 1 = 5 . 0 v v c c 1 = 3 . 0 v 50 20 ms ms 0 . 5 2
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 33 table 5.4 a-d conversion characteristics (1) standard min. t y p .m a x . C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r bits v r e f = v c c 1 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nunit an0 to an7 input an0_0 to an0_7 input an2_0 to an2_7 input anex0, anex1 input v r e f = v c c 1 = 5 v lsb 3 l s b 7 lsb v ref =v cc1 =3.3v 8 b i t 2 r ladder t conv ladder resistance conversion time(10bit), sample & hold function available reference voltage analog input voltage k ? s v v i a v ref v 0 2.0 10 v cc1 v r e f 40 2.75 conversion time(8bit), sample & hold function available s 2 . 3 3 t c o n v t s a m p sampling time 0 . 2 5 s v ref =v cc1 v ref =v cc1 =5v, ? ad=12mhz v r e f = v c c 1 = 5 v , ? a d = 1 2 m h z dnl differential non-linearity error offset error gain error C C lsb lsb lsb 1 3 3 notes: 1. referenced to v cc1 =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at t opr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2. if v cc1 > v cc2 , do not use an0_0 to an0_7 and an2_0 to an2_7 as analog input pins. 3. ad operation clock frequency ( ? ad frequency) must be 12 mhz or less. and divide the fad if v cc1 is less than 4.0v, and ? ad frequency into 10 mhz or less. 4. a case without sample & hold function turn ? ad frequency into 250 khz or more in addition to a limit of note 3. a case with sample & hold function turn ? ad frequency into 1mhz or more in addition to a limit of note 3. 1 0 b i t v r e f = v c c 1 = 3 . 3 v l s b 5 l s b 7 v r e f = v c c 1 = 5 v l s b 3 l s b 7 l s b v r e f = v c c 1 = 3 . 3 v 8 b i t 2 10 bit v r e f = v c c 1 = 3 . 3 v l s b 5 lsb 7 C a b s o l u t e a c c u r a c y external operation amp connection mode an0 to an7 input an0_0 to an0_7 input an2_0 to an2_7 input anex0, anex1 input external operation amp connection mode an0 to an7 input an0_0 to an0_7 input an2_0 to an2_7 input anex0, anex1 input external operation amp connection mode an0 to an7 input an0_0 to an0_7 input an2_0 to an2_7 input anex0, anex1 input external operation amp connection mode tolerance level impedance C 3k ? table 5.5 d-a conversion characteristics (1) min. typ. max. C C ? ma i v r e f 1.0 1 . 5 8 3 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nunit 2 0 1 0 4 s ( n o t e 2 ) standard n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v r e f = 3 . 3 t o 5 . 5 v , v s s = a v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 . t h i s a p p l i e s w h e n u s i n g o n e d - a c o n v e r t e r , w i t h t h e d - a r e g i s t e r f o r t h e u n u s e d d - a c o n v e r t e r s e t t o 0 0 h . t h e a - d c o n v e r t e r s l a d d e r r e s i s t a n c e i s n o t i n c l u d e d . a l s o , w h e n d - a r e g i s t e r c o n t e n t s a r e n o t 0 0 h , t h e c u r r e n t i v r e f a l w a y s f l o w s e v e n t h o u g h v r e f m a y h a v e b e e n s e t t o b e u n c o n n e c t e d b y t h e a - d c o n t r o l r e g i s t e r .
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 34 table 5.6 flash memory version electrical characteristics (1) for 100 cycle products (d3, d5, u3, u5) min. typ. max. word program time (v cc1 =5.0v, t opr =25 c) b l o c k e r a s e t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) e r a s e a l l u n l o c k e d b l o c k s t i m e ( 2 ) l o c k b i t p r o g r a m t i m e p a r a m e t e ru n i t s t a n d a r d 2 5 0 . 3 2 5 2 0 0 2 0 0 s s s s 4 x n f l a s h m e m o r y c i r c u i t s t a b i l i z a t i o n w a i t t i m e t ps 1 5 s - - - - s y m b o l n o t e s : 1 .r e f e r e n c e d t o v c c 1 = 4 . 5 t o 5 . 5 v , 3 . 0 t o 3 . 6 v a t t o p r = 0 t o 6 0 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 .n d e n o t e s t h e n u m b e r o f b l o c k e r a s e s . 3 .p r o g r a m a n d e r a s e e n d u r a n c e r e f e r s t o t h e n u m b e r o f t i m e s a b l o c k e r a s e c a n b e p e r f o r m e d . i f t h e p r o g r a m a n d e r a s e e n d u r a n c e i s n ( n = 1 0 0 , 1 , 0 0 0 , o r 1 0 , 0 0 0 ) , e a c h b l o c k c a n b e e r a s e d n t i m e s . f o r e x a m p l e , i f a 4 k b y t e s b l o c k a i s e r a s e d a f t e r w r i t i n g 1 w o r d d a t a 2 , 0 4 8 t i m e s , e a c h t o a d i f f e r e n t a d d r e s s , t h i s c o u n t s a s o n e p r o g r a m a n d e r a s e e n d u r a n c e . d a t a c a n n o t b e w r i t t e n t o t h e s a m e a d d r e s s m o r e t h a n o n c e w i t h o u t e r a s i n g t h e b l o c k . ( r e w r i t e p r o h i b i t e d ) 4 .m a x i m u m n u m b e r o f e / w c y c l e s f o r w h i c h o p e r a t i o n i s g u a r a n t e e d . 5 .t o p r = - 4 0 t o 8 5 c ( d 3 , d 7 , u 3 , u 7 ) / - 2 0 t o 8 5 c ( d 5 , d 9 , u 5 , u 9 ) . 6 .r e f e r e n c e d t o v c c 1 = 2 . 7 t o 5 . 5 v a t t o p r = - 2 0 t o 8 5 c ( d 9 , u 9 ) / - 4 0 t o 8 5 c ( d 7 , u 7 ) u n l e s s o t h e r w i s e s p e c i f i e d . 7 .t a b l e 5 . 7 a p p l i e s f o r b l o c k a o r b l o c k 1 p r o g r a m a n d e r a s e e n d u r a n c e > 1 , 0 0 0 . o t h e r w i s e , u s e t a b l e 5 . 6 . 8 .t o r e d u c e t h e n u m b e r o f p r o g r a m a n d e r a s e e n d u r a n c e w h e n w o r k i n g w i t h s y s t e m s r e q u i r i n g n u m e r o u s r e w r i t e s , w r i t e t o u n u s e d w o r d a d d r e s s e s w i t h i n t h e b l o c k i n s t e a d o f r e w r i t e . e r a s e b l o c k o n l y a f t e r a l l p o s s i b l e a d d r e s s e s a r e u s e d . f o r e x a m p l e , a n 8 - w o r d p r o g r a m c a n b e w r i t t e n 2 5 6 t i m e s m a x i m u m b e f o r e e r a s e b e c o m e s n e c e s s a r y . m a i n t a i n i n g a n e q u a l n u m b e r o f e r a s u r e b e t w e e n b l o c k a a n d b l o c k 1 w i l l a l s o i m p r o v e e f f i c i e n c y . i t i s i m p o r t a n t t o t r a c k t h e t o t a l n u m b e r o f t i m e s e r a s u r e i s u s e d . 9 .s h o u l d e r a s e e r r o r o c c u r d u r i n g b l o c k e r a s e , a t t e m p t t o e x e c u t e c l e a r s t a t u s r e g i s t e r c o m m a n d , t h e n b l o c k e r a s e c o m m a n d a t l e a s t t h r e e t i m e s u n t i l e r a s e e r r o r d i s a p p e a r s . 1 0 .c u s t o m e r s d e s i r i n g e / w f a i l u r e r a t e i n f o r m a t i o n s h o u l d c o n t a c t t h e i r r e n e s a s t e c h n i c a l s u p p o r t r e p r e s e n t a t i v e . p r o g r a m a n d e r a s e e n d u r a n c e ( 3 ) - 100 4 k b y t e s b l o c k 8 k b y t e s b l o c k 3 2 k b y t e s b l o c k 6 4 k b y t e s b l o c k d a t a h o l d t i m e ( 5 ) 1 0y e a r - 0 . 3 0 . 5 0 . 8 s s s min. typ. max. w o r d p r o g r a m t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) b l o c k e r a s e t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) l o c k b i t p r o g r a m t i m e p a r a m e t e ru n i t standard 25 0 . 3 2 5 s s s - - - s y m b o l p r o g r a m a n d e r a s e e n d u r a n c e ( 3 , 8 , 9 ) - 1 0 , 0 0 0 ( 4 ) 4 k b y t e s b l o c k flash memory circuit stabilization wait time t ps s d a t a h o l d t i m e ( 5 ) 1 0y e a r - c y c l e cycle 15 4 4 4 4 table 5.8 flash memory version program/erase voltage and read operation voltage characteristics (at t opr = 0 to 60 o c) flash program, erase voltage flash read operation voltage v cc1 = 3.3 v 0.3 v or 5.0 v 0.5 v v cc1 =2.7 to 5.5 v table 5.7 flash memory version electrical characteristics (6) for 10,000 cycle products (d7, d9, u7, u7) (block a and block 1 (7) )
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 35 table 5.9 low voltage detection circuit electrical characteristics (1 ) s y m b o l s t a n d a r d t y p . unit measuring condition m i n .max. p a r a m e t e r v d e t 4 vo l t a g e d o w n d e t e c t i o n v o l t a g e ( 1 ) v 3 . 84.4 v c c 1 = 0 . 8 t o 5 . 5 v no t e s: 1 . v d e t 4 > v d e t 3 > v d e t 2 . 2 . w h e r e r e s e t l e v e l d e t e c t i o n v o l t a g e i s l e s s t h a n 2 . 7 v , i f t h e s u p p l y p o w e r v o l t a g e i s g r e a t e r t h a n t h e r e s e t l e v e l d e t e c t i o n v o l t a g e , t h e o p e r a t i o n a t f ( b c l k ) 1 0 m h z i s g u a r a n t e e d . 3 . v d e t 3 r > v d e t 3 i s n o t g u a r a n t e e d . 3 . 3 v d e t 3 r e s e t l e v e l d e t e c t i o n v o l t a g e ( 1 , 2 ) v 2 . 83.6 2 . 2 v d e t 2 r a m r e t e n t i o n l i m i t d e t e c t i o n v o l t a g e ( 1 ) v 2.7 0 . 8 2 . 94.0 2 . 0 s y m b o l s t a n d a r d t y p . unit measuring condition m i n .max. p a r a m e t e r 2 v cc1 =2.7 to 5.5v n o t e s : 1 . w h e n v c c 1 = 5 v . 1 5 0 6 ( 1 ) 5 0 t d ( r - s ) s t o p r e l e a s e t i m e 2 0 t d(m-l) t i m e f o r i n t e r n a l p o w e r s u p p l y s t a b i l i z a t i o n w h e n m a i n c l o c k o s c i l l a t i o n s t a r t s 2 0 t d ( s - r ) h a r d w a r e r e s e t 2 r e l e a s e w a i t t i m e s ms v d e t 3 s l o w v o l t a g e r e s e t r e t e n t i o n v o l t a g e v d e t 3 r l o w v o l t a g e r e s e t r e l e a s e v o l t a g e ( 3 ) 2 . 2 1. 4 v v t d ( p - r ) t i m e f o r i n t e r n a l p o w e r s u p p l y s t a b i l i z a t i o n d u r i n g p o w e r i n g - o n t d ( e - a ) l o w v o l t a g e d e t e c t i o n c i r c u i t o p e r a t i o n s t a r t t i m e s s m s v cc1 =2.7 to 5.5v v c c 1 = v d e t 3 r t o 5 . 5 v t d ( w - s ) l o w p o w e r d i s s i p a t i o n m o d e w a i t m o d e r e l e a s e t i m e 1 5 0 s interrupt for stop mode release cpu clock t d(r-s) t d(s-r) v det3r v cc1 table 5.10 power supply circuit timing characteristics
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 36 v cc1 = v cc2 = 5v table 5.11 electrical characteristics (1 ) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e v o l v o l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e standard t y p . unit m e a s u r i n g c o n d i t i o n v v v xout v 2.0 0 . 4 5 v v x o u t 2.0 2.0 m i n .m a x . v cc2 -2.0 p a r a m e t e r i o h = - 5 m a ( 2 ) i oh =-1ma i o h = - 2 0 0 a ( 2 ) i o h = - 0 . 5 m a i o l = 5 m a ( 2 ) i o l = 1 m a i o l = 2 0 0 a ( 2 ) i o l = 0 . 5 m a p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , h i g h p o w e r lowpower h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h o u t p u t v o l t a g e x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2 . 5 1 . 6 v hysteresis h y s t e r e s i s h i g h i n p u t c u r r e n t i ih low input current i il v r a m r a m r e t e n t i o n v o l t a g e v t + - v t - v t + - v t - sda0 to sda2, clk0 to clk4,ta0out to ta4out, 0 . 21.0v 0.2 2.5 v 5.0 a a a t s t o p m o d e2 . 0v reset h o l d , r d y , t a 0 i n t o t a 4 i n , a d t r g , c t s 0 t o c t s 2 , s c l 0 t o s c l 2 , v i =5v v i =0v -5.0 r f x i n r fxcin f e e d b a c k r e s i s t a n c ex i n feedback resistance xcin 15 1.5 m ? m ? p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset, cnvss, byte p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , x i n , r e s e t , c n v s s , b y t e r p u l l u p pull-up resistance 5 0k ? tb0in to tb5in, int0 to int5, nmi, v xcout 0 0 w i t h n o l o a d a p p l i e d with no load applied highpower l o w p o w e r v i =0v 3 01 7 0 k i 0 t o k i 3 , r x d 0 t o r x d 2 , s i n 3 , s i n 4 p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v cc2 -0.3 v cc1 -2.0 v cc1 -2.0 n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 4 . 2 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 4 m h z u n l e s s o t h e r w i s e s p e c i f i e d . 2 . w h e r e t h e p r o d u c t i s u s e d a t v c c 1 = 5 v a n d v c c 2 = 3 v , r e f e r t o t h e 3 v v e r s i o n v a l u e f o r t h e p i n s p e c i f i e d v a l u e o n t h e v c c 2 p o r t s i d e . 3 . t h e r e i s n o e x t e r n a l c o n n e c t i o n s f o r p o r t p 1 _ 0 t o p 1 _ 7 , p 4 _ 4 t o p 4 _ 7 , p 7 _ 2 t o p 7 _ 5 a n d p 9 _ 1 i n 8 0 - p i n v e r s i o n . v c c 2 v c c 2 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , i o h = - 5 m a i o h = - 2 0 0 a p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, v cc1 -2.0 v cc1 -0.3 v c c 1 v c c 1 v c c 1 v c c 1 p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , i o l = 5 m a i o l = 2 0 0 a 2.0 0 . 4 5 l o w o u t p u t v o l t a g e low output voltage h y s t e r e s i s v t + - v t - xin 0.2 0.8 v
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 37 v cc1 = v cc2 = 5v table 5.12 electrical characteristics (2) (1 ) s y m b o l s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r i cc power supply current (v cc1 =4.0 to 5.5v) n o d i v i s i o n , p l l o p e r a t i o n m a in single-chip mode, the output pins are open and other pins are v ss 14 2 0 f ( b c l k ) = 2 4 m h z , n o d i v i s i o n , p l l o p e r a t i o n m a 18 f ( b c l k ) = 2 4 m h z , m as k rom 2 7 fl as h memory 1 5m a fl as h memory p rogram v c c 1 = 5 . 0 v f ( b c l k ) = 1 0 m h z , 2 5m a fl as h memory e rase v c c 1 = 5 . 0 v f ( b c l k ) = 1 0 m h z , t o p r =2 5 c 3.0 a s t o p m o d e , f(bclk)=32khz, w a i t m o d e ( 2 ) , o s c i l l a t i o n c a p a c i t y h i g h 7.5 a 0.8 2.0 a m a s k r o m f l a s h m e m o r y no t e s: 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 4 . 2 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 4 m h z u n l e s s o t h e r w i s e s p e c i f i e d . 2 . w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . 3 . t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . 4 . i d e t i s d i s s i p a t i o n c u r r e n t w h e n t h e f o l l o w i n g b i t i s s e t t o 1 ( d e t e c t i o n c i r c u i t e n a b l e d ) . i d e t 4 : v c 2 7 b i t o f v c r 2 r e g i s t e r i d e t 3 : v c 2 6 b i t o f v c r 2 r e g i s t e r i d e t 2 : v c 2 5 b i t o f v c r 2 r e g i s t e r m a 1 . 8 wait mode a l o w p o w e r d i s s i p a t i o n m o d e , r o m ( 3 ) f ( x c i n ) = 3 2 k h z , a m as k rom l o w p o w e r d i s s i p a t i o n m o d e , r a m ( 3 ) f ( b c l k ) = 3 2 k h z 420 a l o w p o w e r d i s s i p a t i o n m o d e , f l a s h m e m o r y ( 3 ) f ( b c l k ) = 3 2 k h z , a fl as h memory 2 5 ring oscillation, 5 0 m a 1 n o d i v i s i o n , r i n g o s c i l l a t i o n 2 5 f(bclk)=32khz, w a i t m o d e ( 2 ) , o s c i l l a t i o n c a p a c i t y l o w i det4 voltage down detection dissipation current (4) 4 a 0.7 i det3 reset area detection dissipation current (4) 8 a 1.2 i det2 ram retention limit detection dissipation current (4) 6 a 1.1 n o d i v i s i o n , r i n g o s c i l l a t i o n
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 38 v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) table 5.14 memory expansion mode and microprocessor mode max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 62.5 25 25 15 15 table 5.13 external clock input (xin input) (note 1) (note 2) (note 3) 40 30 0 0 40 0 1. calculated according to the bclk frequency as follows: min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (for setting with no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (for setting with wait) data input access time (when accessing multiplex bus area) f(bclk) C 45 0.5 x 10 9 [ns] 2. calculated according to the bclk frequency as follows: f(bclk) C 45 (n C 0.5) x 10 9 [ns] 3. calculated according to the bclk frequency as follows: f(bclk) C 45 (n C 0.5) x 10 9 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. n is 2 for 2-wait setting, 3 for 3-wait setting. notes:
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 39 v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) table 5.16 timer a input (gating input in timer mode) table 5.17 timer a input (external trigger input in one-shot timer mode) table 5.18 timer a input (external trigger input in pulse width modulation mode) table 5.19 timer a input (counter increment/decrement input in event counter mode) table 5.15 timer a input (counter input in event counter mode) standard max. ns taiin input low pulse width t w(tal) min. ns ns unit taiin input high pulse width t w(tah) parameter symbol t c(ta) taiin input cycle time 40 100 40 standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter taiin input high pulse width taiin input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin - up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter taiin input cycle time taiout input setup time taiin input setup time t c(ta) t su(tain-taout) t su(taout-tain) 800 200 200 table 5.20 timer a input (two-phase pulse input in event counter mode)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 40 table 5.21 timer b input (counter input in event counter mode) table 5.22 timer b input (pulse period measurement mode) table 5.23 timer b input (pulse width measurement mode) table 5.24 a-d trigger input table 5.25 serial i/o _______ table 5.26 external interrupt inti input v cc1 = v cc2 = 5v standard max. min. tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) tbiin input cycle time (counted on both edges) 100 40 40 80 80 200 standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbiin input high pulse width tbiin input cycle time tbiin input low pulse width 400 200 200 standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbiin input cycle time tbiin input high pulse width tbiin input low pulse width 400 200 200 standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit adtrg input cycle time (trigger able minimum) adtrg input low pulse width 1000 125 ns ns ns ns ns ns ns standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 200 100 100 0 30 90 80 standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width 250 250 timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 41 table 5.27 memory expansion and microprocessor modes (for setting with no wait) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) s y m b o l standard measuring condition m a x . min. p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e2 5n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e 15 n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m e C C C cr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) 2. calculated according to the bclk frequency as follows: f(bclk) 0 . 5 x 1 0 9 [ns] f ( b c l k ) i s 1 2 . 5 m h z o r l e s s . C figure 5.1 p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 figure 5.1 ports p0 to p14 measurement circuit
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 42 table 5.28 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) s y m b o l standard measuring condition m a x . m i n . p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e2 5n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e15n s t h(bclk-ale) ale signal output hold time C C 0.5) x 10 9 C C cr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) 2. calculated according to the bclk frequency as follows: f ( b c l k ) 0 . 5 x 1 0 9 [ n s ] n i s 1 f o r 1 - w a i t s e t t i n g , 2 f o r 2 - w a i t s e t t i n g a n d 3 f o r 3 - w a i t s e t t i n g . w h e n n = 1 , f ( b c l k ) i s 1 2 . 5 m h z o r l e s s . C figure 5.1
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 43 table 5.29 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = ?20 to 85 o c / ?40 to 85 o c unless otherwise specified) py t h(bclk-ad) address output hold time (refers to bclk) 4 ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns ns t h(rd-ad) address output hold time (refers to rd) (note 1) t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns ns t h(wr-ad) address output hold time (refers to wr) (note 1) t d(bclk-wr) wr signal output delay time 25 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t d(db-wr) data output delay time (refers to wr) (note 2) ns t h(bclk-wr) wr signal output hold time 0 ns ns t h(rd-cs) chip select output hold time (refers to rd) (note 1) t h(wr-cs) chip select output hold time (refers to wr) (note 1) ns t h(wr-db) data output hold time (refers to wr) ns (note 1) 1. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] 2. calculated according to the bclk frequency as follows: f(bclk) (n C 0.5) x 10 9 C 40 [ns] 3. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C 25 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. t d(bclk-ale) ale signal output delay time (refers to bclk) 15 ns t h(bclk-ale) ale signal output hold time (refers to bclk) C 4ns t h(ale-ad) ale signal output hold time (refers to adderss) ns t d(ad-rd) rd signal output delay from the end of adress ns 0 t d(ad-wr) wr signal output delay from the end of adress ns 0 t dz(rd-ad) address output floating start time ns 8 t d(ad-ale) ale signal output delay time (refers to address) ns (note 3) (note 4) C 10 4. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] C 15 notes: hlda output delay time 40 ns t d(bclk-hlda) see figure 5.1
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 44 taiin input taiout input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(tin C up) t su(up C tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) tbiin input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) adtrg input t c(ta) t su(tain-taout) t su(taout-tain) t su(taout-tain) two-phase pulse input in event counter mode taiin input taiout input t su(tain-taout) xin input t w(h) t w(l) t r t f t c figure 5.2 timing diagram (1)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) v cc1 = v cc2 = 5v 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 45 figure 5.3 timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 46 figure 5.4 timing diagram (3) measuring conditions : ? v cc1 =v cc2 =5v ? input timing voltage : determined with v il =1.0v, v ih =4.0v ? output timing voltage : determined with v ol =2.5v, v oh =2.5v memory expansion mode, microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 (1) ( common to setting with wait and setting without wait ) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclk C hold) t su(hold C bclk) ( effective for setting with wait ) t d(bclk C hlda) t d(bclk C hlda) hi C z rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) v cc1 = v cc2 = 5v 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 47 bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 x tcyc-45)ns.max t cyc= 1 f(bclk) (0.5 x tcyc-10)ns.min (0.5 x tcyc-10)ns.min figure 5.5 timing diagram (4)
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 48 bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min t cyc bhe read timing wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min (0.5 x tcyc-10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc-10)ns.min t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v (1.5 x tcyc-45)ns.max t cyc= f(bclk) 1 figure 5.6 timing diagram (5)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) v cc1 = v cc2 = 5v 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 49 figure 5.7 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc-10)ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (2.5 x tcyc-45)ns.max t cyc= 1 f(bclk)
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 50 figure 5.8 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc-10)ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (3.5 x tcyc-45)ns.max t cyc= 1 f(bclk)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) v cc1 = v cc2 = 5v 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 51 figure 5.9 timing diagram (8) memory expansion mode, microprocessor mode ( for 1- or 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 x tcyc-10)ns.min address data input 40ns.min (0.5 x tcyc-10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc-10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 x tcyc-25)ns.min (1.5 x tcyc-40)ns.min (0.5 x tcyc-10)ns.min t d(bclk-ale) (0.5 x tcyc-25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 x tcyc-10)ns.min (0.5 x tcyc-15)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t h(ale-ad) (1.5 x tcyc-45)ns.max t cyc= 1 f(bclk)
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 52 figure 5.10 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe bclk csi ale adi /dbi t cyc t d(bclk-ad) 25ns.max t cyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 x tcyc-10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t h(wr-db) (0.5 x tcyc-10)ns.min data input address address adi bhe wr, wrl wrh measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t d(ad-ale) (0.5 x tcyc-25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max aaaa (0.5 x tcyc-10)ns.min t h(wr-cs) t d(db-wr) (2.5 x tcyc-40)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 x tcyc-10)ns.min t d(ad-ale) (0.5 x tcyc-25)ns.min (2.5 x tcyc-45)ns.max t cyc= 1 f(bclk) (no multiplex) (no multiplex) t h(ale-ad) (0.5 x tcyc-15)ns.min t h(bclk-ale) -4ns.min
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 53 table 5.30 electrical characteristics ( 1) s y m b o l v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v v x o u t v v x o u t 0 . 5 0 . 5 min. m a x . v c c 2 - 0 . 5 p a r a m e t e r i o h = - 1 m a i o h = - 0 . 1 m a i oh = - 50 a i o l = 1 m a i o l = 0 . 1 m a i o l = 5 0 a p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 highpower l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2 . 5 1.6 v h y s t e r e s i s h y s t e r e s i s high input current i i h l o w i n p u t c u r r e n t i i l v ram r a m r e t e n t i o n v o l t a g e v t+- v t- v t + - v t - 0 . 20 . 8v 0 . 21 . 8v p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , 4 . 0 a a a t s t o p m o d e2 . 0v r e s e t x i n , r e s e t , c n v s s , b y t e v i = 3 v v i = 0 v - 4 . 0 r f x i n r f x c i n f e e d b a c k r e s i s t a n c ex i n f e e d b a c k r e s i s t a n c ex c i n 2 5 3.0 m ? m ? r pullup p u l l - u p r e s i s t a n c e 100 k ? v x c o u t 0 0 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d h i g h p o w e r l o w p o w e r v i = 0 v 50 500 s d a 0 t o s d a 2 , c l k 0 t o c l k 4 , t a 0 o u t t o t a 4 o u t , h o l d , r d y , t a 0 i n t o t a 4 i n , adtrg, cts0 to cts2, scl0 to scl2, t b 0 i n t o t b 5 i n , i n t 0 t o i n t 5 , n m i , ki0 to ki3, rxd0 to rxd2, sin3, sin4 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , x i n , r e s e t , c n v s s , b y t e p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 v c c 1 - 0 . 5 v c c 1 - 0 . 5 n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 2 . 7 t o 3 . 3 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . 2 . v c c 1 f o r t h e p o r t p 6 t o p 1 1 a n d p 1 4 , a n d v c c 2 f o r t h e p o r t p 0 t o p 5 a n d p 1 2 t o p 1 3 . 3 . t h e r e i s n o e x t e r n a l c o n n e c t i o n s f o r p o r t p 1 _ 0 t o p 1 _ 7 , p 4 _ 4 t o p 4 _ 7 , p 7 _ 2 t o p 7 _ 5 a n d p 9 _ 1 i n 8 0 - p i n v e r s i o n . v c c 2 v c c 1 v c c 1 0 . 5 ( 0 . 7 ) h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , i o h = - 1 m a ( 2 ) v c c 1 - 0 . 5 v c c 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , i o l = 1 m a ( 2 ) 0 . 5 h y s t e r e s i s v t + - v t - 0 . 20 . 8v x i n
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 54 table 5.31 electrical characteristics (2) ( 1) s y m b o l s t a n d a r d t y p . u n i t measuring condition m i n .m a x . parameter no division m a in single-chip mode, the output pins are open and other pins are v ss 8 1 1 f ( b c l k ) = 1 0 m h z , no division m a f ( b c l k ) = 1 0 m h z , m a s k r o m 1 3 f l a s h m e m o r y m a 1 . 8 m a 1 n o d i v i s i o n , r i n g o s c i l l a t i o n i c c p o w e r s u p p l y c u r r e n t ( v c c 1 = 2 . 7 t o 3 . 6 v ) t opr =25 c 3.0 a stop mode, f(bclk)=32khz, wait mode (2) , oscillation capacity high 6.0 a 0 . 7 1.8 a mask rom flash memory n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 2 . 7 t o 3 . 3 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . 2 . w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . 3 . t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . 4 . i d e t i s d i s s i p a t i o n c u r r e n t w h e n t h e f o l l o w i n g b i t i s s e t t o 1 ( d e t e c t i o n c i r c u i t e n a b l e d ) . i d e t 4 : v c 2 7 b i t o f v c r 2 r e g i s t e r i d e t 3 : v c 2 6 b i t o f v c r 2 r e g i s t e r i d e t 2 : v c 2 5 b i t o f v c r 2 r e g i s t e r wait mode a l o w p o w e r d i s s i p a t i o n m o d e , r o m ( 3 ) f(xcin)=32khz, a m as k rom low power dissipation mode, ram (3) f ( b c l k ) = 3 2 k h z , 4 2 0 a low power dissipation mode, flash memory (3) f(bclk)=32khz, a fl as h memory 2 5 ri n g o s c i l l a t i o n , 45 2 5 f(bclk)=32khz, w a i t m o d e ( 2 ) , o s c i l l a t i o n c a p a c i t y l o w i d e t 4 v o l t a g e d o w n d e t e c t i o n d i s s i p a t i o n c u r r e n t ( 4 ) 4 a 0.6 i d e t 3 r e s e t l e v e l d e t e c t i o n d i s s i p a t i o n c u r r e n t ( 4 ) 2 a 0.4 i d e t 2 ram retention limit detection dissipation current (4) 4 a 0 . 9 n o d i v i s i o n , r i n g o s c i l l a t i o n 8 v c c 1 = 3 . 0 v m a f l a s h m e m o r y 1 2 f ( b c l k ) = 1 0 m h z , p r o g r a m v c c 1 = 3 . 0 v m a f l a s h m e m o r y 2 2 f ( b c l k ) = 1 0 m h z , e r a s e
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 55 timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 5.33 memory expansion and microprocessor modes table 5.32 external clock input (xin input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18 (note 1) (note 2) (note 3) 50 40 0 0 50 0 1. calculated according to the bclk frequency as follows: min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (for setting with no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (for setting with wait) data input access time (when accessing multiplex bus area) f(bclk) C 60 0.5 x 10 9 [ns] 2. calculated according to the bclk frequency as follows: f(bclk) C 60 (n C 0.5) x 10 9 [ns] 3. calculated according to the bclk frequency as follows: f(bclk) C 60 (n C 0.5) x 10 9 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. n is 2 for 2-wait setting, 3 for 3-wait setting. notes:
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 56 timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 5.34 timer a input (counter input in event counter mode) standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter taiin input high pulse width taiin input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter taiin input cycle time taiout input setup time taiin input setup time t c(ta) t su(tain-taout) t su(taout-tain) 2 500 500 standard max. ns taiin input low pulse width t w(tal) min. ns ns unit taiin input high pulse width t w(tah) parameter symbol t c(ta) taiin input cycle time 60 150 60 table 5.35 timer a input (gating input in timer mode) table 5.36 timer a input (external trigger input in one-shot timer mode) table 5.37 timer a input (external trigger input in pulse width modulation mode) table 5.38 timer a input (counter increment/decrement input in event counter mode) table 5.39 timer a input (two-phase pulse input in event counter mode)
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 57 table 5.40 timer b input (counter input in event counter mode) table 5.41 timer b input (pulse period measurement mode) table 5.42 timer b input (pulse width measurement mode) table 5.43 a-d trigger input table 5.44 serial i/o _______ table 5.45 external interrupt inti input ns ns unit standard max. min. tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) tbiin input cycle time (counted on both edges) 150 60 60 120 120 300 standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbiin input high pulse width tbiin input cycle time tbiin input low pulse width 600 300 300 standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbiin input cycle time tbiin input high pulse width tbiin input low pulse width 600 300 300 standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit adtrg input cycle time (trigger able minimum) adtrg input low pulse width 1500 200 t w(inh) t w(inl) symbol parameter inti input low pulse width inti input high pulse width standard max. min. 380 380 ns ns ns ns ns ns ns standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 300 150 150 0 50 90 160 timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified)
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 58 switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) figure 5.11 ports p0 to p14 measurement circuit table 5.46 memory expansion, microprocessor modes (for setting with no wait) s y m b o l s t a n d a r d measuring condition max. min. parameter u n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e30n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e25n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m e C C C cr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) 2. calculated according to the bclk frequency as follows: f(bclk) 0 . 5 x 1 0 9 [ns] f ( b c l k ) i s 1 2 . 5 m h z o r l e s s . C figure 5.11 p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 59 table 5.47 memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) s y m b o l s t a n d a r d measuring condition m a x . m i n . p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e3 0n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( r e f e r s t o b c l k )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e2 5n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m e C C 0 . 5 ) x 1 0 9 C C cr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. d b i r c (note 1) (note 2) 2 . c a l c u l a t e d a c c o r d i n g t o t h e b c l k f r e q u e n c y a s f o l l o w s : f ( b c l k ) 0 . 5 x 1 0 9 [ n s ] n i s 1 f o r 1 - w a i t s e t t i n g , 2 f o r 2 - w a i t s e t t i n g a n d 3 f o r 3 - w a i t s e t t i n g . w h e n n = 1 , f ( b c l k ) i s 1 2 . 5 m h z o r l e s s . C figure 5.11
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 60 switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, unless otherwise specified) table 5.48 memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 50 ns t h(bclk-ad) address output hold time (refers to bclk) 4 ns t d(bclk-cs) chip select output delay time 50 ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns ns t h(rd-ad) address output hold time (refers to rd) (note 1) t d(bclk-rd) rd signal output delay time 40 ns t h(bclk-rd) rd signal output hold time 0 ns ns t h(wr-ad) address output hold time (refers to wr) (note 1) t d(bclk-wr) wr signal output delay time 40 ns t d(bclk-db) data output delay time (refers to bclk) 50 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t d(db-wr) data output delay time (refers to wr) (note 2) ns t h(bclk-wr) wr signal output hold time 0 ns ns t h(rd-cs) chip select output hold time (refers to rd) t h(wr-cs) chip select output hold time (refers to wr) (note 1) ns t h(wr-db) data output hold time (refers to wr) ns (note 1) 1. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] 2. calculated according to the bclk frequency as follows: f(bclk) (n C 0.5) x 10 9 C 50 [ns] 3. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C 40 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. (note 1) t d(bclk-ale) ale signal output delay time (refers to bclk) 25 ns t h(bclk-ale) ale signal output hold time (refers to bclk) C 4ns t h(ale-ad) ale signal output hold time (refers to adderss) ns t d(ad-rd) rd signal output delay from the end of address ns 0 t d(ad-wr) wr signal output delay from the end of address ns 0 t dz(rd-ad) address output floating start time ns 8 t d(ad-ale) ale signal output delay time (refers to address) ns (note 3) (note 4) C 10 4. calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C 15 [ns] notes: hlda output delay time t d(bclk-hlda) 40 ns see figure 5.11
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 61 figure 5.12 timing diagram (1) taiin input taiout input during event counter mode tbiin input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin C up) t su(up C tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) adtrg input t c(ta) t su(tain-taout) t su(taout-tain) t su(taout-tain) two-phase pulse input in event counter mode taiin input taiout input t su(tain-taout) xin input t w(h) t w(l) t r t f t c
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 62 figure 5.13 timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 63 figure 5.14 timing diagram (3) measuring conditions : ? v cc1 =v cc2 =3v ? input timing voltage : determined with v il =0.6v, v ih =2.4v ? output timing voltage : determined with v ol =1.5v, v oh =1.5v memory expansion mode, microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 (1) (common to setting with wait and setting without wait) t h(bclk C hold) t su(hold C bclk) (effective for setting with wait) t d(bclk C hlda) t d(bclk C hlda) hi C z rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register.
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 64 figure 5.15 timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 x tcyc-60)ns.max t cyc= 1 f(bclk) (0.5 x tcyc-10)ns.min (0.5 x tcyc-10)ns.min
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 65 figure 5.16 timing diagram (5) bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t h(bclk-ale) -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 50ns.min t h(rd-db) 0ns.min t cyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min (0.5 x tcyc-10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc-10)ns.min t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v (1.5 x tcyc-60)ns.max t cyc= 1 f(bclk)
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 66 figure 5.17 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc-10)ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t ac2(rd-db) (2.5 x tcyc-60)ns.max t cyc= 1 f(bclk)
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 67 figure 5.18 timing diagram (7) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd t cyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc-10)ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t ac2(rd-db) (3.5 x tcyc-60)ns.max t cyc= 1 f(bclk)
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 68 figure 5.19 timing diagram (8) memory expansion mode, microprocessor mode ( for 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 x tcyc-10)ns.min address data input 50ns.min (0.5 x tcyc-10)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc-10)ns.min t h(wr-cs) address t d(ad-ale) (0.5 x tcyc-40)ns.min (1.5 x tcyc-50)ns.min (0.5 x tcyc-10)ns.min t d(bclk-ale) (0.5 x tcyc-40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 x tcyc-10)ns.min t h(ale-ad) t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v (1.5 x tcyc-60)ns.max t cyc= 1 f(bclk) (0.5 x tcyc-15)ns.min
v cc1 = v cc2 = 3v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62p) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 69 figure 5.20 timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /dbi adi bhe bclk csi ale adi /dbi t cyc t d(bclk-ad) 40ns.max t cyc data output t h(bclk-cs) 6ns.min t d(bclk-cs) 40ns.max t d(bclk-ale) 40ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 40ns.max t h(bclk-rd) 0ns.min t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 x tcyc-10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 40ns.max t d(bclk-ad) 40ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 x tcyc-10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 40ns.max t d(bclk-wr) 40ns.max t h(wr-db) (0.5 x tcyc-10)ns.min data input address address adi bhe wr, wrl wrh measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t h(ale-ad) t d(ad-ale) (0.5 x tcyc-40)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 50ns.max (0.5 x tcyc-10)ns.min t h(wr-cs) t d(db-wr) (2.5 x tcyc-50)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 x tcyc-10)ns.min t d(ad-ale) (0.5 x tcyc-40)ns.min (2.5 x tcyc-60)ns.max t cyc= 1 f(bclk) t h(bclk-ale) -4ns.min (no multiplex) (no multiplex) (0.5 x tcyc-15)ns.min
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 70 table 5.49 absolute maximum ratings 5.2 electrical characteristics (m16c/62pt) operating ambient temperature p a r a m e t e runit v r e f , x i n i n p u t v o l t a g e a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e o u t p u t v o l t a g e x o u t v o - 0 . 3 t o v c c 1 + 0 . 3 ( 1 ) -0.3 to v cc1 +0.3 (1) p d p o w e r d i s s i p a t i o n storage temperature r a t e d v a l u e v v v condition v i a v c c v c c 1 , v c c 2 t s t g t opr s y m b o l m w p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 7 _ 0 , p 7 _ 1 p 7 _ 0 , p 7 _ 1 -0.3 to 6.5 v v r e s e t , c n v s s , b y t e , v cc1 =av cc v cc1 =av cc -0.3 to 6.5 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , s u p p l y v o l t a g e - 0 . 3 t o v c c 1 + 0 . 1 v v c c 2 v cc2 p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 - 0 . 3 t o v c c 2 + 0 . 3 ( 1 ) v v p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 0 t o p 1 1 _ 7 , p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 -0.3 to v cc2 +0.3 (1) v -0.3 to 6.5 -65 to 150 300 -40 to 85 / -40 to 125 (2) -0.3 to 6.5 -40 o c < t opr 85 c n o t e s : 1 . t h e r e i s n o e x t e r n a l c o n n e c t i o n s f o r p o r t p 1 _ 0 t o p 1 _ 7 , p 4 _ 4 t o p 4 _ 7 , p 7 _ 2 t o p 7 _ 5 a n d p 9 _ 1 i n 8 0 - p i n v e r s i o n . 2 . t v e r s i o n = - 4 0 t o 8 5 c , v v e r s i o n = - 4 0 t o 1 2 5 c . - 4 0 o c < t o p r 1 2 5 c 20 0 0 to 60 when the microcomputer is operating f l a s h p r o g r a m e r a s e p14_0, p14_1, c c
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 71 table 5.50 recommended operating conditions (1) 4.0 5.5 t y p .m a x . unit p a r a m e t e r v c c 1 , v c c 2 5 . 0 s u p p l y v o l t a g e ( v c c 1 = v c c 2 ) symbol m i n . s t a n d a r d a n a l o g s u p p l y v o l t a g e v c c 1 a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h i o h ( a v g ) h i g h a v e r a g e o u t p u t c u r r e n t m a m a v s s a v s s 0.8v cc2 v v v v v cc2 0 . 2 v c c 2 0 . 2 v c c 1 0 0 l o w i n p u t v o l t a g e i o h ( p e a k ) h i g h p e a k o u t p u t c u r r e n t h i g h i n p u t v o l t a g e -5.0 - 1 0 . 0 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 3 _ 1 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 v 0 . 8 v c c 2 v cc2 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 ( d u r i n g s i n g l e - c h i p m o d e ) low peak output current 10.0 5.0 ma f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y low average output current i o l ( p e a k ) m a i ol (avg) v p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 7 _ 0 , p 7 _ 1 0.8v cc1 6.5 v v i l v c c 1 = 4 . 0 t o 5 . 5 v 0m h z 1 6 f (xcin) sub-clock oscillation frequency khz 50 32.768 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 notes: 1. referenced to v cc1 = v cc2 = 4.7 to 5.5v at topr = -40 to 85 c / -40 to 125 c unless otherwise specified. t version = -40 to 85 c, v version = -40 to 125 c. 2. the mean output current is the mean value within 100ms. 3. the total i ol(peak) for ports p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14_0 and p14_1 must be 80ma max. the total i ol(peak) for ports p3, p4, p5, p6, p7, p8_0 to p8_4, p12, and p13 must be 80ma max. the total i oh(peak) for ports p0, p1, and p2 must be -40ma max. the total i oh(peak) for ports p3, p4, p5, p12, and p13 must be -40ma max. the total i oh(peak) for ports p6, p7, and p8_0 to p8_4 must be -40ma max. the total i oh(peak) for ports p8_6, p8_7, p9, p10, p11, p14_0, and p14_1 must be -40ma max. as for 80-pin version, the total i ol(peak) for all ports and i oh(peak) must be 80ma. max. due to one v cc and one v ss . 4. there is no external connections for port p1_0 to p1_7, p4_4 to p4_7, p7_2 to p7_5 and p9_1 in 80-pin version. 0.8v cc1 v v cc1 p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , x i n , r e s e t , c n v s s , b y t e p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , p 3 _ 1 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 ( d u r i n g s i n g l e - c h i p m o d e ) v 0 . 2 v c c 2 0 p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , x i n , r e s e t , c n v s s , b y t e p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , f (ring) ring oscillation frequency mhz 1 f (pll) pll clock oscillation frequency (4) v cc1 =4.0 to 5.5v 10 mhz 24 f (bclk) cpu operation clock 0 mhz 24 t s u ( p l l ) p l l f r e q u e n c y s y n t h e s i z e r s t a b i l i z a t i o n w a i t t i m ev c c 1 = 5 . 0 v20m s 0 . 5 2
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 72 table 5.51 a-d conversion characteristics (1) table 5.52 d-a conversion characteristics (1) s t a n d a r d m i n .t y p .m a x . C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r b i t s v r e f = v c c 1 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t a n 0 t o a n 7 i n p u t a n 0 _ 0 t o a n 0 _ 7 i n p u t a n 2 _ 0 t o a n 2 _ 7 i n p u t a n e x 0 , a n e x 1 i n p u t v r e f = v c c 1 = 5 v l s b 3 l s b 7 l s b v r e f = v c c 1 = 3 . 3 v 8 b i t 2 r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e ( 1 0 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e r e f e r e n c e v o l t a g e a n a l o g i n p u t v o l t a g e k ? s v v i a v r e f v 0 2. 0 1 0 v c c 1 v r e f 4 0 2 . 7 5 c o n v e r s i o n t i m e ( 8 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e s 2 . 3 3 t c o n v t s a m p s a m p l i n g t i m e0 . 2 5 s v r e f = v c c 1 v r e f = v c c 1 = 5 v , ? a d = 1 2 m h z v r e f = v c c 1 = 5 v , ? a d = 1 2 m h z d n l d i f f e r e n t i a l n o n - l i n e a r i t y e r r o r o f f s e t e r r o r g a i n e r r o r C C l s b l s b l s b 1 3 3 1 0 b i t v r e f = v c c 1 = 5 v l s b 3 l s b 7 l s b v r e f = v c c 1 = 3 . 3 v 8 b i t 2 1 0 b i t C a b s o l u t e a c c u r a c y e x t e r n a l o p e r a t i o n a m p c o n n e c t i o n m o d e a n 0 t o a n 7 i n p u t a n 0 _ 0 t o a n 0 _ 7 i n p u t a n 2 _ 0 t o a n 2 _ 7 i n p u t a n e x 0 , a n e x 1 i n p u t e x t e r n a l o p e r a t i o n a m p c o n n e c t i o n m o d e t o l e r a n c e l e v e l i m p e d a n c e C 3k ? n o t e s : 1 . r e f e r e n c e d t o v c c 1 = a v c c = v r e f = 4 . 0 t o 5 . 5 v , v s s = a v s s = 0 v a t t o p r = - 4 0 t o 8 5 c / - 4 0 t o 1 2 5 c u n l e s s o t h e r w i s e s p e c i f i e d . t v e r s i o n = - 4 0 t o 8 5 c , v v e r s i o n = - 4 0 t o 1 2 5 c . 2 . a d o p e r a t i o n c l o c k f r e q u e n c y ( ? a d f r e q u e n c y ) m u s t b e 1 2 m h z o r l e s s . 3 . a c a s e w i t h o u t s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 2 5 0 k h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 2 . a c a s e w i t h s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 1 m h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 2 . m i n .t y p .m a x . C C ? m a i v r e f 1.0 1 . 5 8 3 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t 2 0 1 0 4 s ( n o t e 2 ) s t a n d a r d n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v r e f = 4 . 0 t o 5 . 5 v , v s s = a v s s = 0 v a t t o p r = - 4 0 t o 8 5 c / - 4 0 t o 1 2 5 c u n l e s s o t h e r w i s e s p e c i f i e d . t v e r s i o n = - 4 0 t o 8 5 c , v v e r s i o n = - 4 0 t o 1 2 5 c 2 . t h i s a p p l i e s w h e n u s i n g o n e d - a c o n v e r t e r , w i t h t h e d - a r e g i s t e r f o r t h e u n u s e d d - a c o n v e r t e r s e t t o 0 0 h . t h e a - d c o n v e r t e r s l a d d e r r e s i s t a n c e i s n o t i n c l u d e d . a l s o , w h e n d - a r e g i s t e r c o n t e n t s a r e n o t 0 0 h , t h e c u r r e n t i v r e f a l w a y s f l o w s e v e n t h o u g h v r e f m a y h a v e b e e n s e t t o b e u n c o n n e c t e d b y t h e a - d c o n t r o l r e g i s t e r .
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 73 table 5.53 flash memory version electrical characteristics (1) for 100 cycle products table 5.55 flash memory version program/erase voltage and read operation voltage characteristics (at t opr = 0 to 60 o c) table 5.54 flash memory version electrical characteristics (6) for 10,000 cycle products (block a and block 1 (7) ) min. typ. m a x . w o r d p r o g r a m t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) b l o c k e r a s e t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) e r a s e a l l u n l o c k e d b l o c k s t i m e ( 2 ) l o c k b i t p r o g r a m t i m e p a r a m e t e runit standard 2 5 0 . 3 2 5 2 0 0 2 0 0 s s s s 4 x n f l a s h m e m o r y c i r c u i t s t a b i l i z a t i o n w a i t t i m e t p s 15 s - - - - s y m b o l p r o g r a m a n d e r a s e e n d u r a n c e ( 3 ) - 100 4 k b y t e s b l o c k 8 k b y t e s b l o c k 3 2 k b y t e s b l o c k 6 4 k b y t e s b l o c k d a t a h o l d t i m e ( 5 ) 10 - 0 . 3 0 . 5 0 . 8 s s s min. typ. max. w o r d p r o g r a m t i m e ( v c c 1 = 5 . 0 v , t o p r = 2 5 c ) block erase time (v cc1 =5.0v, t opr =25 c) l o c k b i t p r o g r a m t i m e parameter unit standard 2 5 0.3 2 5 s s s - - - symbol p r o g r a m a n d e r a s e e n d u r a n c e ( 3 , 8 , 9 ) - 1 0 , 0 0 0 ( 4 ) 4k bytes block flash memory circuit stabilization wait time t p s s data hold time (5) 10 - cycle cy c l e 15 4 4 4 4 y e a r year n o t e s : 1 .r e f e r e n c e d t o v c c 1 = 4 . 5 t o 5 . 5 v a t t o p r = 0 t o 6 0 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 .n d e n o t e s t h e n u m b e r o f b l o c k e r a s e s . 3 .p r o g r a m a n d e r a s e e n d u r a n c e r e f e r s t o t h e n u m b e r o f t i m e s a b l o c k e r a s e c a n b e p e r f o r m e d . i f t h e p r o g r a m a n d e r a s e e n d u r a n c e i s n ( n = 1 0 0 , 1 , 0 0 0 , o r 1 0 , 0 0 0 ) , e a c h b l o c k c a n b e e r a s e d n t i m e s . f o r e x a m p l e , i f a 4 k b y t e s b l o c k a i s e r a s e d a f t e r w r i t i n g 1 w o r d d a t a 2 , 0 4 8 t i m e s , e a c h t o a d i f f e r e n t a d d r e s s , t h i s c o u n t s a s o n e p r o g r a m a n d e r a s e e n d u r a n c e . d a t a c a n n o t b e w r i t t e n t o t h e s a m e a d d r e s s m o r e t h a n o n c e w i t h o u t e r a s i n g t h e b l o c k . ( r e w r i t e p r o h i b i t e d ) 4 .m a x i m u m n u m b e r o f e / w c y c l e s f o r w h i c h o p e r a t i o n i s g u a r a n t e e d . 5 .t o p r = - 4 0 t o 8 5 c (t v e r s i o n) / - 4 0 t o 1 2 5 c ( v v e r s i o n ) . 6 .r e f e r e n c e d t o v c c 1 = 4 . 0 t o 5 . 5 v a t t o p r = - 4 0 t o 8 5 c ( t v e r s i o n ) / - 4 0 t o 1 2 5 c ( v v e r s i o n ) u n l e s s o t h e r w i s e s p e c i f i e d . 7 .t a b l e 5 . 5 5 a p p l i e s f o r b l o c k a o r b l o c k 1 p r o g r a m a n d e r a s e e n d u r a n c e > 1 , 0 0 0 . o t h e r w i s e , u s e t a b l e 5 . 5 4 . 8 .t o r e d u c e t h e n u m b e r o f p r o g r a m a n d e r a s e e n d u r a n c e w h e n w o r k i n g w i t h s y s t e m s r e q u i r i n g n u m e r o u s r e w r i t e s , w r i t e t o u n u s e d w o r d a d d r e s s e s w i t h i n t h e b l o c k i n s t e a d o f r e w r i t e . e r a s e b l o c k o n l y a f t e r a l l p o s s i b l e a d d r e s s e s a r e u s e d . f o r e x a m p l e , a n 8 - w o r d p r o g r a m c a n b e w r i t t e n 2 5 6 t i m e s m a x i m u m b e f o r e e r a s e b e c o m e s n e c e s s a r y . m a i n t a i n i n g a n e q u a l n u m b e r o f e r a s u r e b e t w e e n b l o c k a a n d b l o c k 1 w i l l a l s o i m p r o v e e f f i c i e n c y . i t i s i m p o r t a n t t o t r a c k t h e t o t a l n u m b e r o f t i m e s e r a s u r e i s u s e d . 9 .s h o u l d e r a s e e r r o r o c c u r d u r i n g b l o c k e r a s e , a t t e m p t t o e x e c u t e c l e a r s t a t u s r e g i s t e r c o m m a n d , t h e n b l o c k e r a s e c o m m a n d a t l e a s t t h r e e t i m e s u n t i l e r a s e e r r o r d i s a p p e a r s . 1 0 .c u s t o m e r s d e s i r i n g e / w f a i l u r e r a t e i n f o r m a t i o n s h o u l d c o n t a c t t h e i r r e n e s a s t e c h n i c a l s u p p o r t r e p r e s e n t a t i v e . flash program, erase voltage flash read operation voltage v cc1 =5.0 0.5 v v cc1 =4.0 to 5.5 v
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 74 table 5.56 power supply circuit timing characteristics s y m b o l s t a n d a r d t y p . u n i t measuring condition min. m a x . p a r a m e t e r 2 v cc1 =4.0 to 5.5v 1 5 0 5 0 t d(r-s) stop release time t d(m-l) time for internal power supply stabilization when main clock oscillation starts ms t d(p-r) time for internal power supply stabilization during powering-on s s t d(w-s) low power dissipation mode wait mode release time 1 5 0 s interrupt for stop mode release cpu clock t d(r-s)
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 75 v cc1 = v cc2 = 5v table 5.57 electrical characteristics (1 ) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e v o l v o l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d typ. u n i t m e a s u r i n g c o n d i t i o n v v v x o u t v 2 . 0 0.45 v v x o u t 2 . 0 2 . 0 m i n .m a x . v cc2 -2.0 p a r a m e t e r i o h = - 5 m a ( 2 ) i o h = - 1 m a i o h = - 2 0 0 a ( 2 ) i o h = - 0 . 5 m a i o l = 5 m a ( 2 ) i o l = 1 m a i o l = 2 0 0 a ( 2 ) i o l = 0 . 5 m a p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h o u t p u t v o l t a g e x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2.5 1.6 v h y s t e r e s i s hysteresis high input current i i h l o w i n p u t c u r r e n t i i l v r a m r a m r e t e n t i o n v o l t a g e v t+- v t- v t+- v t- s d a 0 t o s d a 2 , c l k 0 t o c l k 4 , t a 0 o u t t o t a 4 o u t , 0.2 1 . 0v 0.2 2.5 v 5 . 0 a a a t s t o p m o d e2 . 0v reset h o l d , r d y , t a 0 i n t o t a 4 i n , a d t r g , c t s 0 t o c t s 2 , s c l 0 t o s c l 2 , v i = 5 v v i = 0 v- 5 . 0 r fxin r f x c i n feedback resistance xin f e e d b a c k r e s i s t a n c e xcin 1 5 1.5 m ? m ? p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xin, reset, cnvss, byte p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 , x i n , r e s e t , c n v s s , b y t e r p u l l u p p u l l - u p r e s i s t a n c e 50 k ? tb0in to tb5in, int0 to int5, nmi, v x c o u t 0 0 with no load applied w i t h n o l o a d a p p l i e d highpower l o w p o w e r v i =0v 30 170 ki0 to ki3, rxd0 to rxd2, sin3, sin4 p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 v cc2 -0.3 v cc1 -2.0 v cc1 -2.0 n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 4 . 0 t o 5 . 5 v , v s s = 0 v a t t o p r = - 4 0 t o 8 5 c / - 4 0 t o 1 2 5 c , f ( b c l k ) = 2 4 m h z u n l e s s o t h e r w i s e s p e c i f i e d . t v e r s i o n i s - 4 0 = 8 5 c , v v e r s i o n = - 4 0 t o 1 2 5 c . 2 . t h e r e i s n o e x t e r n a l c o n n e c t i o n s f o r p o r t p 1 _ 0 t o p 1 _ 7 , p 4 _ 4 t o p 4 _ 7 , p 7 _ 2 t o p 7 _ 5 a n d p 9 _ 1 i n 8 0 - p i n v e r s i o n . v c c 2 v c c 2 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , i oh =-5ma i o h = - 2 0 0 a p 6 _ 0 t o p 6 _ 7 , p 7 _ 2 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p14_0, p14_1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , v cc1 -2.0 v cc1 -0.3 v c c 1 v c c 1 v c c 1 v c c 1 p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p 4 _ 0 t o p 4 _ 7 , p 5 _ 0 t o p 5 _ 7 , p 1 2 _ 0 t o p 1 2 _ 7 , p 1 3 _ 0 t o p 1 3 _ 7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , p 6 _ 0 t o p 6 _ 7 , p 7 _ 0 t o p 7 _ 7 , p 8 _ 0 t o p 8 _ 4 , p 8 _ 6 , p 8 _ 7 , p4_0 to p4_7, p5_0 to p5_7, p12_0 to p12_7, p13_0 to p13_7 p 9 _ 0 t o p 9 _ 7 , p 1 0 _ 0 t o p 1 0 _ 7 , p 1 1 _ 0 t o p 1 1 _ 7 , p 1 4 _ 0 , p 1 4 _ 1 p 0 _ 0 t o p 0 _ 7 , p 1 _ 0 t o p 1 _ 7 , p 2 _ 0 t o p 2 _ 7 , p 3 _ 0 t o p 3 _ 7 , i o l = 5 m a i o l = 2 0 0 a 2 . 0 0.45 l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e h y s t e r e s i s v t + - v t - x i n 0.2 0 . 8v
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 76 v cc1 = v cc2 = 5v table 5.58 electrical characteristics (2) (1 ) s y m b o l s t a n d a r d typ. unit measuring condition m i n .m a x . p a r a m e t e r i c c p o w e r s u p p l y c u r r e n t ( v c c 1 = 4 . 0 t o 5 . 5 v ) no division, pll operation m a in single-chip mode, the output pins are open and other pins are v ss 14 20 f(bclk)=24mhz, no division, pll operation m a 1 8 f(bclk)=24mhz, m as k rom 2 7 fl as h memory 15 m a fl as h memory p rogram v cc1 =5.0v f(bclk)=10mhz, 2 5m a fl as h memory e rase v cc1 =5.0v f(bclk)=10mhz, t opr =25 c 3 . 0 a stop mode, f(bclk)=32khz, wait mode (2) , oscillation capacity high 7 . 5 a 0 . 8 2 . 0 a m a s k r o m f l a s h m e m o r y n o t e s : 1 . r e f e r e n c e d t o v c c 1 = v c c 2 = 4 . 0 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 4 m h z u n l e s s o t h e r w i s e s p e c i f i e d . t v e r s i o n = - 4 0 t o 8 5 c , v v e r s i o n = - 4 0 t o 1 2 5 c 2 . w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . 3 . t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . 4 . i d e t i s d i s s i p a t i o n c u r r e n t w h e n t h e f o l l o w i n g b i t i s s e t t o 1 ( d e t e c t i o n c i r c u i t e n a b l e d ) . i d e t 4 : v c 2 7 b i t o f v c r 2 r e g i s t e r i d e t 3 : v c 2 6 b i t o f v c r 2 r e g i s t e r i d e t 2 : v c 2 5 b i t o f v c r 2 r e g i s t e r m a 1 . 8 wait mode a low power dissipation mode, rom (3) f(xcin)=32khz, a m a s k r o m low power dissipation mode, ram (3) f(bclk)=32khz 420 a low power dissipation mode, flash memory (3) f(bclk)=32khz, a f l a s h m e m o r y 2 5 ring oscillation, 50 ma 1 no division, ring oscillation 2 5 f(bclk)=32khz, wait mode (2) , oscillation capacity low i d e t 4 voltage down detection dissipation current (4) 4 a 0.7 i d e t 3 reset area detection dissipation current (4) 8 a 1.2 i d e t 2 ram retention limit detection dissipation current (4) 6 a 1 . 1 no division, ring oscillation
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 77 v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = 40 to 85 o c (t version) / 40 to 125 o c (v version) unless otherwise specified) table 5.59 external clock input (xin input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 62.5 25 25 15 15
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 78 v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = 40 to 85 o c (t version) / 40 to 125 o c (v version) unless otherwise specified) table 5.61 timer a input (gating input in timer mode) table 5.62 timer a input (external trigger input in one-shot timer mode) table 5.63 timer a input (external trigger input in pulse width modulation mode) table 5.64 timer a input (counter increment/decrement input in event counter mode) table 5.60 timer a input (counter input in event counter mode) table 5.65 timer a input (two-phase pulse input in event counter mode) standard max. ns taiin input low pulse width t w(tal) min. ns ns unit taiin input high pulse width t w(tah) parameter symbol t c(ta) taiin input cycle time 40 100 40 standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit taiin input cycle time taiin input high pulse width taiin input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter taiin input high pulse width taiin input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin - up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter taiin input cycle time taiout input setup time taiin input setup time t c(ta) t su(tain-taout) t su(taout-tain) 800 200 200
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 79 table 5.66 timer b input (counter input in event counter mode) table 5.67 timer b input (pulse period measurement mode) table 5.68 timer b input (pulse width measurement mode) table 5.69 a-d trigger input table 5.70 serial i/o _______ table 5.71 external interrupt inti input v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = 40 to 85 o c (t version) / 40 to 125 o c (v version) unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) tbiin input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbiin input high pulse width tbiin input cycle time tbiin input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbiin input cycle time tbiin input high pulse width tbiin input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit adtrg input cycle time (trigger able minimum) adtrg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 80 v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = 40 to 85 o c (t version) / 40 to 125 o c (v version) unless otherwise specified) figure 5.21 ports p0 to p10 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf
m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) v cc1 = v cc2 = 5v 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 81 figure 5.22 timing diagram (1) taiin input taiout input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(tin C up) t su(up C tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) tbiin input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) adtrg input t c(ta) t su(tain-taout) t su(taout-tain) t su(taout-tain) two-phase pulse input in event counter mode taiin input taiout input t su(tain-taout) xin input t w(h) t w(l) t r t f t c
v cc1 = v cc2 = 5v m16c/62 group (m16c/62p, m16c/62pt) 5. electrical characteristics (m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 82 figure 5.23 timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
package dimensions m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 83 package dimensions qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m mmp qfp80-p-1414-0.65 1.11 weight(g) jedec code eiaj package code lead material alloy 42 80p6s-a plastic 80pin 14 ? 14mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.65 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 80 61 40 60 41 21 20 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f x 0.13 b x m mmp
package dimensions m16c/62 group (m16c/62p, m16c/62pt) 4 8 f o 3 0 0 2 , 7 0 . v o n 0 1 . 2 . v e r page 84 m d l 2 b 2 m e e recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 y b x m lp a3 lqfp128-p-1420-0.50 weight(g) jedec code eiaj package code lead material cu alloy 128p6q-a plastic 128pin 14 ? 20mm body lqfp 1.5 0.125 1.4 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 1.0 i 2 m d 14.4 m e 20.4 8 0 0.1 1.0 0.65 0.5 0.35 22.2 22.0 21.8 16.2 16.0 15.8 0.5 20.1 20.0 19.9 14.1 14.0 13.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0.05 1.7 e e e c h e 1 38 39 64 65 h d d a f a 1 a 2 l 1 l detail f 128 103 102 mmp lqfp100-p-1414-0.50 weight(g) 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 76 75 51 50 26 25 h d d a f y 100 lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c m d l 2 b 2 m e e recommended mount pad mmp
revision history rev. date description page summary a-1 m16c/62 group (m16c/62p, m16c/62pt) data sheet 1.10 may/28/y03 (continued) 2.00 oct./29/y03 table 1.1.1 is partly revised. table 1.1.2 and 1.1.3 is partly revised. sfr is partly revised. note 1 is partly revised. table 1.5.3 is partly revised. table 1.5.5 is partly revised. table 1.5.6 is added. table 1.5.9 is partly revised. notes 1 and 2 in table 1.5.26 is partly revised. notes 1 in table 1.5.27 is partly revised. note 3 is added to data output hold time (refers to bclk) in table 1.5.26 and 1.5.27. note 4 is added to th(ale-ad) in table 1.5.28. switching characteristics is partly revised. th(wr-ad) and th(wr-db) in figure 1.5.5 to 1.5.8 is partly revised. th(ale-ad), th(wr-cs), th(wr-db) and th(wr-ad) in figure 1.5.9 to 1.5.10 is partly revised. note 2 is added to table 1.5.29. notes 1 and 2 in table 1.5.45 is partly revised. notes 1 in table 1.5.46 is partly revised. note 3 is added to data output hold time (refers to bclk) in table 1.5.45 and 1.5.46. note 4 is added to th(ale-ad) in table 1.5.47. switching characteristics is partly revised. th(wr-ad) and th(wr-db) in figure 1.5.15 to 1.5.18 is partly revised. th(ale-ad), th(wr-cs), th(wr-db) and th(wr-ad) in figure 1.5.19 to 1.5.20 is partly revised. since high reliability version is added, a group name is revised. m16c/62 group (m16c/62p) ? m16c/62 group (m16c/62p, m16c/62pt) table 1.1 to 1.3 are revised. note 3 is partly revised. figure 1.2 note5 is deleted. table 1.4 to 1.7 product list is partly revised. table 1.8 and figure 1.4 are added. figure 1.5 to 1.9 zp is added. table 1.10 and 1.12 zp is added to timer a. table 1.11 and 1.13 vcc1 is added to vref. table 5.1 is revised. table 5.2 and 5.3 are revised. table 5.4 a-d conversion characteristics is revised. table 5.5 d-a conversion characteristics revised. table 5.6 to 5.7 and table 5.54 to 5.55 are revised. table 5.11 is revised. table 5.14 and 5.33 hlda output deley time is deleted. figure 5.1 is partly revised. table 5.27 to 5.29 and table 5.46 to 48 hlda output deley time is added. figure 5.2 timing diagram (1) x in input is added. 2 4-5 14-19 22 23 24 30 31 30-31 32 30-32 36-39 40-41 42 47 48 47-48 49 47-49 53-56 57-58 - 2-4 6 7-9 11 12-15 17,19 18,20 30 31-32 33 34,74 36 38,55 41 41-43, 58-60 44
revision history rev. date description page summary a-2 m16c/62 group (m16c/62p, m16c/62pt) data sheet figure 5.5 to 5.6 read timing db --> dbi figure 5.7 to 5.8 write timing db --> dbi figure 5.10 db --> dbi table 5.30 is revised. figure 5.11 is partly revised. figure 5.12 timing diagram (1) x in input is added. figure 5.15 to 5.16 read timing db --> dbi figure 5.17 to 5.18 write timing db --> dbi figure 5.20 db --> dbi electrical characteristics (m16c/62pt) is added. 47-48 49-50 52 53 58 61 64-65 66-67 69 70-85 2.10 nov./07/y03 table 1.5 to 1.7 product list is partly revised. note 1 is deleted. table 3.1 is revised. table 5.50 is revised. table 5.51 is deleted. 8-9 23 71 72
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